From patchwork Tue Apr 21 15:11:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Delaunay X-Patchwork-Id: 238202 List-Id: U-Boot discussion From: patrick.delaunay at st.com (Patrick Delaunay) Date: Tue, 21 Apr 2020 17:11:19 +0200 Subject: [PATCH 0/9] stm32mp1: use OPP information for PLL1 settings in SPL Message-ID: <20200421151128.18072-1-patrick.delaunay@st.com> This serie allows to switch the CPU frequency to the max frequency supported in OPP device tree nodes and supported by STM32MP SOC (800MHz is supported by STM32MP15xD and STM32MP15xF). Board also increases the VDDCore voltage to support this new operation point. Marek Vasut (1): ARM: stm32: Add board_early_init_f() to SPL Patrick Delaunay (8): arm: stm32mp: spl: add bsec driver in SPL ARM: dts: stm32: add cpufreq support on stm32mp15x board: st: create common file stpmic1.c stm32mp1: clk: configure pll1 with OPP arm: stm32mp: add weak function to save vddcore board: st: stpmic1: add function stmpic_buck1_set board: stm32mp1: update vddcore in SPL ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL arch/arm/dts/stm32mp15-u-boot.dtsi | 12 +- arch/arm/dts/stm32mp151.dtsi | 21 ++ arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 9 - arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 9 - arch/arm/dts/stm32mp157c-ed1.dts | 8 + arch/arm/dts/stm32mp15xx-dkx.dtsi | 8 + arch/arm/mach-stm32mp/Makefile | 2 +- arch/arm/mach-stm32mp/bsec.c | 11 +- .../arm/mach-stm32mp/include/mach/sys_proto.h | 3 + arch/arm/mach-stm32mp/spl.c | 11 + board/dhelectronics/dh_stm32mp1/Makefile | 2 +- board/st/common/Makefile | 1 + board/st/common/stpmic1.c | 186 +++++++++++ board/st/common/stpmic1.h | 6 + board/st/stm32mp1/board.c | 158 ---------- board/st/stm32mp1/spl.c | 20 ++ .../clock/st,stm32mp1.txt | 4 + drivers/clk/clk_stm32mp1.c | 295 ++++++++++++++++-- 18 files changed, 554 insertions(+), 212 deletions(-) create mode 100644 board/st/common/stpmic1.c create mode 100644 board/st/common/stpmic1.h