mbox series

[v3,00/17] mtd: spi-nor-core: add xSPI Octal DTR support

Message ID 20200330154550.21179-1-p.yadav@ti.com
Headers show
Series mtd: spi-nor-core: add xSPI Octal DTR support | expand

Message

Pratyush Yadav March 30, 2020, 3:45 p.m. UTC 
Hi,

This series adds support for octal DTR flashes in the spi-nor framework,
and then adds hooks for the Cypress Semper flash which is an xSPI
compliant Octal DTR flash.

The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.

Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
u-boot-ti/next.

This series depends on [0].

[0] cf. <20200224071051.19331-1-p.yadav at ti.com>
[0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html

Changes in v3:
- Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
  tripping up controllers.
- Use op->data.nbytes as a measure of whether the data phase exists or
  not. This fixes data buswidth not being updadted for SR and FSR reads
  because they keep data buffer as NULL when calling spi_nor_setup_op().
- Add support for Micron mt35xu512aba to run in Octal DTR mode.

Pratyush Yadav (17):
  spi: spi-mem: allow specifying whether an op is DTR or not
  spi: spi-mem: allow specifying a command's extension
  spi: cadence-qspi: Do not calibrate when device tree sets read delay
  spi: cadence-qspi: Add support for octal DTR flashes
  mtd: spi-nor-core: Add a ->setup() hook
  mtd: spi-nor-core: Move SFDP related declarations to top
  mtd: spi-nor-core: Introduce flash-specific fixup hooks
  mtd: spi-nor-core: Rework hwcaps selection
  mtd: spi-nor-core: Add support for DTR protocol
  mtd: spi-nor-core: Get command opcode extension type from BFPT
  mtd: spi-nor-core: Parse xSPI Profile 1.0 table
  mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
  mtd: spi-nor-core: Enable octal DTR mode when possible
  mtd: spi-nor-core: Perform a Soft Reset on shutdown
  mtd: spi-nor-core: Perform a Soft Reset on boot
  mtd: spi-nor-core: Add support for Cypress Semper flash
  mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode

 drivers/mtd/spi/Kconfig        |   11 +
 drivers/mtd/spi/sf_internal.h  |   13 +
 drivers/mtd/spi/sf_probe.c     |    9 +
 drivers/mtd/spi/spi-nor-core.c | 1273 +++++++++++++++++++++++++-------
 drivers/mtd/spi/spi-nor-ids.c  |    3 +-
 drivers/mtd/spi/spi-nor-tiny.c |   22 -
 drivers/spi/cadence_qspi.c     |   87 ++-
 drivers/spi/cadence_qspi.h     |   15 +-
 drivers/spi/cadence_qspi_apb.c |  286 ++++++-
 drivers/spi/spi-mem.c          |    3 +
 include/linux/mtd/spi-nor.h    |  271 +++++--
 include/spi-mem.h              |   16 +-
 12 files changed, 1619 insertions(+), 390 deletions(-)

--
2.25.0

Comments

Jagan Teki May 12, 2020, 4:43 p.m. UTC | #1 
On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav <p.yadav at ti.com> wrote:
>
> Hi,
>
> This series adds support for octal DTR flashes in the spi-nor framework,
> and then adds hooks for the Cypress Semper flash which is an xSPI
> compliant Octal DTR flash.
>
> The Cadence QSPI controller driver is also updated to run in Octal DTR
> mode.
>
> Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
> u-boot-ti/next.
>
> This series depends on [0].
>
> [0] cf. <20200224071051.19331-1-p.yadav at ti.com>
> [0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html
>
> Changes in v3:
> - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
>   tripping up controllers.
> - Use op->data.nbytes as a measure of whether the data phase exists or
>   not. This fixes data buswidth not being updadted for SR and FSR reads
>   because they keep data buffer as NULL when calling spi_nor_setup_op().
> - Add support for Micron mt35xu512aba to run in Octal DTR mode.

Do you have foot-print statistics for these changes? if yes can mark it here.

Jagan.
Pratyush Yadav May 12, 2020, 6:23 p.m. UTC | #2 
On 12/05/20 10:13PM, Jagan Teki wrote:
> On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav <p.yadav at ti.com> wrote:
> >
> > Hi,
> >
> > This series adds support for octal DTR flashes in the spi-nor framework,
> > and then adds hooks for the Cypress Semper flash which is an xSPI
> > compliant Octal DTR flash.
> >
> > The Cadence QSPI controller driver is also updated to run in Octal DTR
> > mode.
> >
> > Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
> > u-boot-ti/next.
> >
> > This series depends on [0].
> >
> > [0] cf. <20200224071051.19331-1-p.yadav at ti.com>
> > [0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html
> >
> > Changes in v3:
> > - Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
> >   tripping up controllers.
> > - Use op->data.nbytes as a measure of whether the data phase exists or
> >   not. This fixes data buswidth not being updadted for SR and FSR reads
> >   because they keep data buffer as NULL when calling spi_nor_setup_op().
> > - Add support for Micron mt35xu512aba to run in Octal DTR mode.
> 
> Do you have foot-print statistics for these changes? if yes can mark it here.

Do you mean binary size difference?

With these changes, the U-Boot binary is 830308 bytes. Without them it 
is 825260 bytes. That is a 5048 byte increase.

With these changes, the SPL binary weighs in at 605312 bytes. Without 
them it is 600488 bytes. That is a 4824 byte increase.

This is with both the Spansion and STMicro configs enabled. When I 
disable them I get the follwing data.

U-Boot:
With: 822644
Without: 819688
Difference: 2956

SPL:
With: 599218
Without: 596192
Difference: 3026