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[81.169.180.215]) by mx.google.com with ESMTP id d33-v6si496162edd.393.2018.11.16.06.04.38; Fri, 16 Nov 2018 06:04:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FNRKNSWI; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 794A2C224F2; Fri, 16 Nov 2018 14:03:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F2F4BC224FC; Fri, 16 Nov 2018 14:02:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CFDAEC2250D; Fri, 16 Nov 2018 14:01:23 +0000 (UTC) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by lists.denx.de (Postfix) with ESMTPS id ADC36C22501 for ; Fri, 16 Nov 2018 14:00:50 +0000 (UTC) Received: by mail-wr1-f66.google.com with SMTP id u5-v6so19712469wrn.9 for ; Fri, 16 Nov 2018 06:00:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=oknPt4ijnieIqJkuELUhHWBAD8irkuU7/iKnFVHJA3Y=; b=FNRKNSWI122KbRewawI34/qfmwjPLGG4/IGwIqU6xgzeSBb8d//N/lLX8MWNSQN95Y 2h9cVltpx6M4k/dBWa2Egkov/pM2c7gIPB7tjRvdqplM83iCFuKQ8OzChEOUKGzbNvKP sNq34kJJ6uPMtY2epJPXeObn7IqvC07SZtv08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=oknPt4ijnieIqJkuELUhHWBAD8irkuU7/iKnFVHJA3Y=; b=cOYgR7rcLm4BtY2e0z8HXhg4RVy9LDl+HJdVPXrnY0tnsTzWkvBjJBRTO03Lt4/GPp 7tKp953MT7NaV2A/DD2w1ESRYxjfn8n4GtajYCaolbs56w2IsxKXS7X8xivxb8QYCX4z NsOYtCnkok0YoRPSPFrZd4dmR7R6RK9S7ynac1y6GZMHJpS7V9jax468kDLmN0I4Cuyo qEWVrCs/GP5R+GNwY4gbHsgtNutuj26bbY3A1mim2yjAjab39hkGAgkzZLsNSc1wGXWE Sd1hdJ7cQ8tAocK/HxQAe4f3lqCfUOhBGd6EyMNJrBMlUXYQXWT7cfjQpA49LYPrsYTO VzpA== X-Gm-Message-State: AGRZ1gKOQdYQHEbscZ2r/1eanXMSJHvqoLkMMUoDMErAYm38tR6AeSTZ PcYcCpXQHaxAeKkZUJWt4+vXgg== X-Received: by 2002:adf:b594:: with SMTP id c20-v6mr9271289wre.137.1542376850170; Fri, 16 Nov 2018 06:00:50 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105d:3df6:606e:fa38:9819:9c69]) by smtp.gmail.com with ESMTPSA id s81sm11208060wmf.14.2018.11.16.06.00.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Nov 2018 06:00:49 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Fri, 16 Nov 2018 15:00:35 +0100 Message-Id: <20181116140039.11628-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v4 0/4] Add Hardware Spinlock class X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" version 4: - make timeout loop more robust version 3: - use dev_get_parent - add Review-by version 2: - use -ETIMEDOUT and -ENOSYS for errors cases - do not test if ops is valid - remove useless include - add a private structure to store base address - be more verbose in configuration flag description and commit message - log the error after hwspinlock_get_by_index() This series add a news class to support hardware spinlock. Hardware spinlock could be used to protect critical sections of code between multi-processors. The proposed API remain simple with only 3 functions to be called client: - hwspinlock_get_by_index: get a hardware spinlock by integer index from device-tree node - hwspinlock_lock_timeout: lock the hardware spinlock - hwspinlock_unlock: unlock the hardware spinlock Driver API offert 4 operations: - of_xlate: translate a client's device-tree (OF) hardware specifier - lock: lock the hardware spinlock - unlock: unlock the hardware spinlock - relax: wait time between two calls to lock operations Benjamin Gaignard (4): dm: Add Hardware Spinlock class clk: stm32: add hardware spinlock clock hwspinlock: add stm32 hardware spinlock support pinctrl: stm32: make pinctrl use hwspinlock arch/arm/dts/stm32mp157c-ed1.dts | 8 ++ arch/arm/dts/stm32mp157c.dtsi | 9 ++ arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 1 + configs/sandbox_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 3 + drivers/hwspinlock/Kconfig | 24 ++++++ drivers/hwspinlock/Makefile | 7 ++ drivers/hwspinlock/hwspinlock-uclass.c | 144 ++++++++++++++++++++++++++++++++ drivers/hwspinlock/sandbox_hwspinlock.c | 56 +++++++++++++ drivers/hwspinlock/stm32_hwspinlock.c | 92 ++++++++++++++++++++ drivers/pinctrl/pinctrl_stm32.c | 27 ++++++ include/dm/uclass-id.h | 1 + include/hwspinlock.h | 140 +++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/hwspinlock.c | 40 +++++++++ 19 files changed, 564 insertions(+) create mode 100644 drivers/hwspinlock/Kconfig create mode 100644 drivers/hwspinlock/Makefile create mode 100644 drivers/hwspinlock/hwspinlock-uclass.c create mode 100644 drivers/hwspinlock/sandbox_hwspinlock.c create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c create mode 100644 include/hwspinlock.h create mode 100644 test/dm/hwspinlock.c