From patchwork Fri Nov 16 10:39:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 151324 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp260012ljp; Fri, 16 Nov 2018 02:40:05 -0800 (PST) X-Google-Smtp-Source: AJdET5eZ8iJooaTNTw6SmLKSj4f1P6kJKtvoDukuiLJZygEgsGHg31vf4DRBIwd0OsyDP85EExNR X-Received: by 2002:a17:906:c401:: with SMTP id u1-v6mr8317596ejz.196.1542364805201; Fri, 16 Nov 2018 02:40:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542364805; cv=none; d=google.com; s=arc-20160816; b=PHwqlfQhNJdOhJDtuE772IrRltDhZnjQnO2QuQuUrpakKiVZso+V1Ra10JXSUL1raE JJclmnRgbnrH//fceQPzGgHiLKkwuSh76KUPGFUaQhMYSvRhnmFsaMNUUc0W0YahoJNm KQNj5Y4u3BelAbx7AYo/vV6nJoLQBcj76WEMKyOF4HMhebxe1Y3ssFz+bfvqzDhahftB dmlysu3eyc7+/up05dDa8jK3D8IvK0cE1EbSC/6L9ohEDkfAsK4lM2wgYxOVSWP5rRY9 mTDun8BAaCQLa1ybiG2lJyvZBFGmqBpX24lxLkp5LWdOBRLCKFtWfVWgeX1hd+Vsh3YZ ZydA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature; bh=cEZr/ZKvcX8soUsIY/uDfR4xowdB5exOzcq2DujoTN4=; b=FPSklbh4QsGvbhEBIY5V/PT22UHbTkDodvBWwx7VpGzvhiF3Uc2mxzXSkOIaNOzbiS uCsQ7YWH1JvogAaWld2LUZ97xRfJmdtFY+D//pW8Xjvo3bNiMophP+SF7plbdi7T7oGX AlOHFgKlfT5HucEzaoN/eCFU1NAhwJeqELWkBAGKBImxGeJrExutw3eUe4WKzzZR2BNe AIhQuXFmpyKtaF3vd9f1/nM4enfL/sbu7IgzXYuuLWqDz/6seUOqY77XIsZWjJG+LF/e cobXheMKFqBQfi6AEV0nH1gg7j7Z3k8k2i0DPiz1KGc4cC76Dt7mxhhzEtkwotBO3cJ6 AZDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LyvogOlf; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id j35si5487215ede.153.2018.11.16.02.40.04; Fri, 16 Nov 2018 02:40:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LyvogOlf; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 8919DC224DC; Fri, 16 Nov 2018 10:40:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DCA4C222CE; Fri, 16 Nov 2018 10:40:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 329EFC222CE; Fri, 16 Nov 2018 10:39:59 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id CF9DAC22045 for ; Fri, 16 Nov 2018 10:39:58 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id f2-v6so20575169wme.3 for ; Fri, 16 Nov 2018 02:39:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=/6Glm2CLqgJq+FQWhYBMTQEOH4byPbPwyHKay00o+2U=; b=LyvogOlfmj2HGsDk+pNod6srD3dlv+SFhCX4WfRIMZkG5jg9qn2dBn7bwLdbdDIl5C 6PKO2jroD8iNAl+XLmmUtUr+bDpFNGukysJ9MdX6WY82/0ZwqSgRQZ29wv+akvh0qCsX tHurRxKoI7iiQde3ID67KrK7SuPfL5+rFBLWw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/6Glm2CLqgJq+FQWhYBMTQEOH4byPbPwyHKay00o+2U=; b=KTw3bKptHYPZrHwMWdK9SAiT54NJCBI1/PRqTBAGEuL8DDTwwxnkCGdIiRFMekb8bE W+SgbP53m0o364kIleuvITWgatOyZG1SByJQ+fGk28MWiiX+ythJTU2npBdy1Xd5uuKr YcrSy9IgTbmpqfMXJyAYfVSSNUYp6jWow1wNrIvARVVRlh7e66iSfYvYut33qBzHoVJc oBft1Anm0s8J6GQJpMap5UYaGYXmdRA6c84zFAw73N3qCdNpwxb1JqiblPBo9AW+k0Mp ib/1sDZ270lLUaem0aonZM0xDsXlS5RF8DN3hwWkTZgXFoIbrGWhaKV4az/lJCVBaGNQ 4C+Q== X-Gm-Message-State: AGRZ1gKu80e7g8DEnGnGCaMBnRPqcQyYYh22DNwXU0RXDbeax90PKZzE tfcslr3SKCp+rCzo89HT3nMolQ== X-Received: by 2002:a1c:b513:: with SMTP id e19-v6mr7955652wmf.114.1542364798355; Fri, 16 Nov 2018 02:39:58 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105d:3df6:606e:fa38:9819:9c69]) by smtp.gmail.com with ESMTPSA id f68sm13960857wmd.15.2018.11.16.02.39.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 16 Nov 2018 02:39:57 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Fri, 16 Nov 2018 11:39:43 +0100 Message-Id: <20181116103947.11002-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH v3 0/4] Add Hardware Spinlock class X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" version 3: - use dev_get_parent - add Review-by version 2: - use -ETIMEDOUT and -ENOSYS for errors cases - do not test if ops is valid - remove useless include - add a private structure to store base address - be more verbose in configuration flag description and commit message - log the error after hwspinlock_get_by_index() This series add a news class to support hardware spinlock. Hardware spinlock could be used to protect critical sections of code between multi-processors. The proposed API remain simple with only 3 functions to be called client: - hwspinlock_get_by_index: get a hardware spinlock by integer index from device-tree node - hwspinlock_lock_timeout: lock the hardware spinlock - hwspinlock_unlock: unlock the hardware spinlock Driver API offert 4 operations: - of_xlate: translate a client's device-tree (OF) hardware specifier - lock: lock the hardware spinlock - unlock: unlock the hardware spinlock - relax: wait time between two calls to lock operations Benjamin Gaignard (4): dm: Add Hardware Spinlock class clk: stm32: add hardware spinlock clock hwspinlock: add stm32 hardware spinlock support pinctrl: stm32: make pinctrl use hwspinlock arch/arm/dts/stm32mp157c-ed1.dts | 8 ++ arch/arm/dts/stm32mp157c.dtsi | 9 ++ arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 1 + configs/sandbox_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 3 + drivers/hwspinlock/Kconfig | 24 ++++++ drivers/hwspinlock/Makefile | 7 ++ drivers/hwspinlock/hwspinlock-uclass.c | 143 ++++++++++++++++++++++++++++++++ drivers/hwspinlock/sandbox_hwspinlock.c | 56 +++++++++++++ drivers/hwspinlock/stm32_hwspinlock.c | 92 ++++++++++++++++++++ drivers/pinctrl/pinctrl_stm32.c | 27 ++++++ include/dm/uclass-id.h | 1 + include/hwspinlock.h | 140 +++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/hwspinlock.c | 40 +++++++++ 19 files changed, 563 insertions(+) create mode 100644 drivers/hwspinlock/Kconfig create mode 100644 drivers/hwspinlock/Makefile create mode 100644 drivers/hwspinlock/hwspinlock-uclass.c create mode 100644 drivers/hwspinlock/sandbox_hwspinlock.c create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c create mode 100644 include/hwspinlock.h create mode 100644 test/dm/hwspinlock.c