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[81.169.180.215]) by mx.google.com with ESMTP id 60-v6si1501526edg.285.2018.11.13.04.18.26; Tue, 13 Nov 2018 04:18:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eInFuDb9; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 7E834C224F2; Tue, 13 Nov 2018 12:16:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 93E88C22503; Tue, 13 Nov 2018 12:15:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5BFB9C21E35; Tue, 13 Nov 2018 08:52:00 +0000 (UTC) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by lists.denx.de (Postfix) with ESMTPS id 0351EC21DCA for ; Tue, 13 Nov 2018 08:52:00 +0000 (UTC) Received: by mail-wr1-f65.google.com with SMTP id 74-v6so12276788wrb.13 for ; Tue, 13 Nov 2018 00:52:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=F37NqDghaVgLSdc8G99NUoRNOKFMwujDMvG7YlInC6s=; b=eInFuDb9FunFObjvvpQsX5RVdCxZ2saA9AjZ95yQSZ7o1YG6AguRnyiZnZqIiJzKEX ecrsbz3ipqEy0Yzk4UNl230WId3QY3lLkOfJqq2N1ZHMmON3uXT7d8FtmUzD9+tZvgBh jPuYBMLC67+BKVYG5LX39eIOEY0SUf05k5Q/c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=F37NqDghaVgLSdc8G99NUoRNOKFMwujDMvG7YlInC6s=; b=aIJKKj6T+H5YagMcFbwQuJnj83X+2dL1xZxR+Dzr0cAB+H7e90jgE8Ot3pSBAtL4y1 rGo/BjsJ7hKmdZVd82x3xUbfnKJADe4PeIfw7/uJ6eDYyoaal2EB74l4sHxtXsWzPgd3 IYrObVnW6fRZIkOaXbYyGq8cm96JP3/z7R5OpUiu0G2qKRE8CNkHst/xFjDbshota8B3 lCTLQv2699iTJuR+MA1UUFQkNIojEJ/6HtXJq9X7R78wy/H68HmRwnNiSkJu48m1TKMV srxoP8vumlayEV8475RQw0uo0CFFgPZv614r972D+GGJLneWOTU/FlaDtWiHVA2xsK8r XDBA== X-Gm-Message-State: AGRZ1gIblVhHuP+ojPQcJV2fnu8cGhNp0eiMMZdVbwE7diSNRUDz+46F CYrG+iSFCVyxeCDvsXdkCB7mnw== X-Received: by 2002:adf:c084:: with SMTP id d4-v6mr4126873wrf.268.1542099119469; Tue, 13 Nov 2018 00:51:59 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1047:8145:8cab:bca7:b2f2:d2bb]) by smtp.gmail.com with ESMTPSA id d18-v6sm4235544wre.25.2018.11.13.00.51.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Nov 2018 00:51:58 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: patrick.delaunay@st.com, albert.u.boot@aribaud.net, sjg@chromium.org, christophe.kerello@st.com, patrice.chotard@st.com Date: Tue, 13 Nov 2018 09:51:47 +0100 Message-Id: <20181113085151.32368-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 X-Mailman-Approved-At: Tue, 13 Nov 2018 12:15:27 +0000 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Benjamin Gaignard Subject: [U-Boot] [PATCH 0/4] Add Hardware Spinlock class X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series add a news class to support hardware spinlock. Hardware spinlock could be used to protect critical sections of code between multi-processors. The proposed API remain simple with only 3 functions to be called client: - hwspinlock_get_by_index: get a hardware spinlock by integer index from device-tree node - hwspinlock_lock_timeout: lock the hardware spinlock - hwspinlock_unlock: unlock the hardware spinlock Driver API offert 4 operations: - of_xlate: translate a client's device-tree (OF) hardware specifier - lock: lock the hardware spinlock - unlock: unlock the hardware spinlock - relax: wait time between two calls to lock operations Benjamin Gaignard (4): dm: Add Hardware Spinlock class clk: stm32: add hardware spinlock clock hwspinlock: add stm32 hardware spinlock support pinctrl: stm32: make pinctrl use hwspinlock arch/arm/dts/stm32mp157c-ed1.dts | 8 ++ arch/arm/dts/stm32mp157c.dtsi | 9 ++ arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 1 + configs/sandbox_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/clk/clk_stm32mp1.c | 3 + drivers/hwspinlock/Kconfig | 22 +++++ drivers/hwspinlock/Makefile | 7 ++ drivers/hwspinlock/hwspinlock-uclass.c | 145 ++++++++++++++++++++++++++++++++ drivers/hwspinlock/sandbox_hwspinlock.c | 56 ++++++++++++ drivers/hwspinlock/stm32_hwspinlock.c | 90 ++++++++++++++++++++ drivers/pinctrl/pinctrl_stm32.c | 22 +++++ include/dm/uclass-id.h | 1 + include/hwspinlock.h | 140 ++++++++++++++++++++++++++++++ test/dm/Makefile | 1 + test/dm/hwspinlock.c | 40 +++++++++ 19 files changed, 556 insertions(+) create mode 100644 drivers/hwspinlock/Kconfig create mode 100644 drivers/hwspinlock/Makefile create mode 100644 drivers/hwspinlock/hwspinlock-uclass.c create mode 100644 drivers/hwspinlock/sandbox_hwspinlock.c create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c create mode 100644 include/hwspinlock.h create mode 100644 test/dm/hwspinlock.c