From patchwork Mon Apr 23 05:59:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 133958 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp619412lji; Sun, 22 Apr 2018 23:05:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx48LwGGJo42brqMdGcqmxcnKgF8lR4DThTPnSeZclaMig798LCsVpwoKKtlw0yXEe1RrDLlh X-Received: by 10.80.245.205 with SMTP id x13mr26143756edm.132.1524463552912; Sun, 22 Apr 2018 23:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524463552; cv=none; d=google.com; s=arc-20160816; b=goxkoM8V1i98vUJ0ssHKAGtKNRgPe544a/UsuvT0T81oT78Dzb+lGNKGNzUdjQJ4CR F5L86BaDv91sbT2aPZJ+ETuunywfrPHpdDvAWQkZDYAvE68I8QKBHQ+s+IiQtrUETBHf 7AZY1gXCNUO7zSdX2jQRMch6Ogx5AlyCAAQqWW+8E8XzNBBeuDHnDxs7LMG8sOCvEppV Y3Gdzo3EBkymijrQnui04TU/gIzN6W4BLy5Ty5H41g/odLQkifgdb7rU+xp6D+zYeIjm +hKLJzyELsPE8+8enOKyfzHP27UcGfwSPAgrk7VwIdgdi/J/Z9qZozYcPeqYVjcHnkgl fRxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :arc-authentication-results; bh=jTxpDzTP/yDsnfhQhEziY0RZX9ZtAZsSe2wnB8veTbY=; b=KvStq4v4jJ8X8YULG3Bg+WgqiS6brmBNEIgaBLLMpYt03d5rpbxsdRmQ9kSwTmz/73 7vZb8BwM22O/3D5RLS1Yr42XAnnwe16S/lkAY6/uG5iEQf9F8ZfL6gSZRZPSPxYln2S6 qyiJQbFqyxwrBs8BZDGxjEL3Y5X/ardCwpoRU+/OYGnGTXWx4Vlmpxod/xAYdxKOylaZ s20jS0JBr7fQ1YAZeBZJl/NoavUT2QAeNcBz7IB1Ia4nTh74P4yoMZZIiFyQCYJuivSp zMsgqyGpbGufbv7wUwq0nbtIz7sPXI7VnszZJLwEuwKF/CcAg7Tj3qLJoX54cjJY/Gxw yvIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id b7si1567884edl.201.2018.04.22.23.05.52; Sun, 22 Apr 2018 23:05:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 7C4B3C21D83; Mon, 23 Apr 2018 06:02:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52844C21D8E; Mon, 23 Apr 2018 06:00:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A75DBC21C6A; Mon, 23 Apr 2018 05:59:51 +0000 (UTC) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by lists.denx.de (Postfix) with ESMTPS id 6B8D0C21DC1 for ; Mon, 23 Apr 2018 05:59:51 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 39957AC21; Mon, 23 Apr 2018 05:59:51 +0000 (UTC) From: Alexander Graf To: u-boot@lists.denx.de Date: Mon, 23 Apr 2018 07:59:42 +0200 Message-Id: <20180423055950.78818-1-agraf@suse.de> X-Mailer: git-send-email 2.12.3 Cc: Heinrich Schuchardt , schwab@suse.de, Greentime Hu Subject: [U-Boot] [PATCH v3 0/8] riscv: Enable efi_loader support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We now have RISC-V support in U-Boot - which is great! However, not that we're finally making progress to converge on efi_loader and distro boot for booting on ARM platforms, we really want to make sure there is no technical reason not to do the same on RISC-V as well. So this patch set introduces distro boot and efi_loader support for RISC-V! So far, I've only tested it with the selftest and hello world target in U-Boot, as the number of target binaries to run is still slim. But it should at least give us a good starting point. v1 -> v2: - Allow 32bit target - Also save/restore ra, sp - Use edk2 default boot file names - Enable hello world binary - remove patch: efi_loader: selftest: Do not build relocation tests for risc-v - new patch: riscv: Add EFI application infrastructure v2 -> v3: - Add missing crt0 source - Use official values for vci Alexander Graf (8): riscv: Add setjmp/longjmp code riscv: Enable function sections riscv: Add EFI application infrastructure riscv: Add board_quiesce_devices stub efi_loader: Use EFI_CACHELINE_SIZE in the image loader too distro: Extend with RISC-V defines riscv: nx25: Enable distro boot efi_loader: Enable RISC-V support arch/riscv/config.mk | 7 +- arch/riscv/cpu/nx25/u-boot.lds | 16 ++++ arch/riscv/include/asm/setjmp.h | 26 ++++++ arch/riscv/include/asm/u-boot-riscv.h | 1 + arch/riscv/lib/Makefile | 12 +++ arch/riscv/lib/bootm.c | 4 + arch/riscv/lib/crt0_riscv_efi.S | 152 ++++++++++++++++++++++++++++++++++ arch/riscv/lib/elf_riscv32_efi.lds | 70 ++++++++++++++++ arch/riscv/lib/elf_riscv64_efi.lds | 70 ++++++++++++++++ arch/riscv/lib/reloc_riscv_efi.c | 97 ++++++++++++++++++++++ arch/riscv/lib/setjmp.S | 66 +++++++++++++++ cmd/Kconfig | 2 +- configs/nx25-ae250_defconfig | 1 + include/config_distro_bootcmd.h | 11 +++ include/configs/nx25-ae250.h | 17 ++++ include/efi_loader.h | 7 ++ lib/efi_loader/Kconfig | 2 +- lib/efi_loader/efi_image_loader.c | 2 +- lib/efi_loader/efi_runtime.c | 48 ++++++++--- 19 files changed, 595 insertions(+), 16 deletions(-) create mode 100644 arch/riscv/include/asm/setjmp.h create mode 100644 arch/riscv/lib/crt0_riscv_efi.S create mode 100644 arch/riscv/lib/elf_riscv32_efi.lds create mode 100644 arch/riscv/lib/elf_riscv64_efi.lds create mode 100644 arch/riscv/lib/reloc_riscv_efi.c create mode 100644 arch/riscv/lib/setjmp.S