U-Boot cmd "cpu detail" shows inconsistent CPU features.
The current "cpu detail" sometimes shows "Microcode" as a feature, which
is not the case with FU540-C000 on HiFive Unleashed board.
Patch 1: add cpu node aliases.
Patch 2: Init CPU information to avoid inconsistent cpu information.
Patch 3: Correctly parse and update mmu-type.
Patch 4: Set L1 Cache feature if either i-cache or d-cache is present
I have picked few dependent patches from Sean's series from here [1]
and [2].
These have applied on mainline U-Boot commit eae62ae8de18 ("Merge tag
'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi")
Patch history:
=============================================
V6:
-Rebase series with master
-Split patch 2 from v5 as suggested i.e init cpu feature in cpu-class.c
as one patch and handle mmu-type check into another.
-Updated Reviewed-by tags
V5:
-Addressed review comments on v4.
1. Removed patch 1 which was for debug message.
2. Updated commit logs with proper information on number of cpu's
3. Additionally used d-cache to set the L1 feature bit.
V4:
1. Rebased the series to mainline commit.
2. Updated dependency list as few patches are now merged.
3. Added U-Boot log of the flow i.e fsbl + fw_payload.bin (Opensbi+U-Boot)
V3:
1. Included the cosmetic change as suggested
s/L1 feature/L1 cache feature/
2. Added Reviewed-By tags
V2:
1. Incorporate review comments from Bin and Sean Anderson.
and dropped 2nd patch as similar work was already done in [1] and [2]
2 Add cpu node aliases to display cpu node's in sequence.
3. Add fix to show mmu as available cpu feature.
4. Check and append L1 cache feature.
V1: Base version
Thanks to Vincent Chen <vincent.chen at sifive.com> for testing the V1
version of this series.
[1] https://patchwork.ozlabs.org/patch/1316066
[2] https://patchwork.ozlabs.org/patch/1316067
All these together is available here:
https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v6
U-Boot log:
===========================================================
U-Boot SPL 2020.07-rc5-00063-g515541f (Jun 26 2020 - 04:44:08 -0700)
Trying to boot from MMC1
U-Boot 2020.07-rc5-00063-g515541f (Jun 26 2020 - 04:44:08 -0700)
CPU: rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM: 8 GiB
MMC: spi at 10050000:mmc at 0: 0
In: serial at 10010000
Out: serial at 10010000
Err: serial at 10010000
Net: eth0: ethernet at 10090000
Hit any key to stop autoboot: 0
=> cpu list
1: cpu at 1 rv64imafdc
2: cpu at 2 rv64imafdc
3: cpu at 3 rv64imafdc
4: cpu at 4 rv64imafdc
=> cpu detail
1: cpu at 1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU
2: cpu at 2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU
3: cpu at 3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU
4: cpu at 4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU
Sagar Shrikant Kadam (4):
riscv: dts: hifive-unleashed-a00: add cpu aliases
uclass: cpu: fix to display proper CPU features
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit
riscv: cpu: check and append L1 cache to cpu features
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++
drivers/cpu/cpu-uclass.c | 3 +++
drivers/cpu/riscv_cpu.c | 17 +++++++++++++----
3 files changed, 20 insertions(+), 4 deletions(-)
U-Boot cmd "cpu detail" shows inconsistent CPU features. The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. Patch 1: add cpu node aliases. Patch 2: Init CPU information to avoid inconsistent cpu information. Patch 3: Correctly parse and update mmu-type. Patch 4: Set L1 Cache feature if either i-cache or d-cache is present I have picked few dependent patches from Sean's series from here [1] and [2]. These have applied on mainline U-Boot commit eae62ae8de18 ("Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi") Patch history: ============================================= V6: -Rebase series with master -Split patch 2 from v5 as suggested i.e init cpu feature in cpu-class.c as one patch and handle mmu-type check into another. -Updated Reviewed-by tags V5: -Addressed review comments on v4. 1. Removed patch 1 which was for debug message. 2. Updated commit logs with proper information on number of cpu's 3. Additionally used d-cache to set the L1 feature bit. V4: 1. Rebased the series to mainline commit. 2. Updated dependency list as few patches are now merged. 3. Added U-Boot log of the flow i.e fsbl + fw_payload.bin (Opensbi+U-Boot) V3: 1. Included the cosmetic change as suggested s/L1 feature/L1 cache feature/ 2. Added Reviewed-By tags V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] and [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature. V1: Base version Thanks to Vincent Chen <vincent.chen at sifive.com> for testing the V1 version of this series. [1] https://patchwork.ozlabs.org/patch/1316066 [2] https://patchwork.ozlabs.org/patch/1316067 All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v6 U-Boot log: =========================================================== U-Boot SPL 2020.07-rc5-00063-g515541f (Jun 26 2020 - 04:44:08 -0700) Trying to boot from MMC1 U-Boot 2020.07-rc5-00063-g515541f (Jun 26 2020 - 04:44:08 -0700) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB MMC: spi at 10050000:mmc at 0: 0 In: serial at 10010000 Out: serial at 10010000 Err: serial at 10010000 Net: eth0: ethernet at 10090000 Hit any key to stop autoboot: 0 => cpu list 1: cpu at 1 rv64imafdc 2: cpu at 2 rv64imafdc 3: cpu at 3 rv64imafdc 4: cpu at 4 rv64imafdc => cpu detail 1: cpu at 1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu at 2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu at 3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu at 4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU Sagar Shrikant Kadam (4): riscv: dts: hifive-unleashed-a00: add cpu aliases uclass: cpu: fix to display proper CPU features riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit riscv: cpu: check and append L1 cache to cpu features arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ drivers/cpu/cpu-uclass.c | 3 +++ drivers/cpu/riscv_cpu.c | 17 +++++++++++++---- 3 files changed, 20 insertions(+), 4 deletions(-)