From patchwork Sat Mar 28 14:25:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 244458 List-Id: U-Boot discussion From: bmeng.cn at gmail.com (Bin Meng) Date: Sat, 28 Mar 2020 07:25:24 -0700 Subject: [PATCH v2 0/5] azure/gitlab/travis: Add more RISC-V boards testing Message-ID: <1585405529-21397-1-git-send-email-bmeng.cn@gmail.com> At presetn only qemu-riscv64 is tested in our CI pipeline. This adds qemu-riscv32 and qemu-riscv{32,64}_spl testing. For Azure/Gitlab, this depends on a new Docker image below: http://patchwork.ozlabs.org/project/uboot/list/?series=166924 The following results are based on the new Docker image. Azure results: https://dev.azure.com/bmeng/GitHub/_build/results?buildId=195&view=results gitlab results: https://gitlab.denx.de/u-boot/custodians/u-boot-x86/pipelines/2548 travis results: https://travis-ci.org/github/lbmeng/u-boot/builds/668014425 Changes in v2: - new patch: "travis: Replace pre-built ARM/ARM64 GRUB images with the one built from source" - new patch: "travis: Build GRUB image for RISC-V 32-bit and 64-bit" - Update travis to add qemu-riscv32 testing - Update travis to add RISC-V SPL testing Bin Meng (5): travis: Replace pre-built ARM/ARM64 GRUB images with the one built from source travis: Build GRUB image for RISC-V 32-bit and 64-bit azure/gitlab/travis: Add qemu-riscv32 testing test/py: Update u_boot_utils.find_ram_base to bypass the low 2MiB memory azure/gitlab/travis: Add RISC-V SPL testing .azure-pipelines.yml | 21 ++++++++ .gitlab-ci.yml | 33 ++++++++++++ .travis.yml | 131 +++++++++++++++++++++++++++++++++++++++++++++--- test/py/u_boot_utils.py | 7 +-- 4 files changed, 183 insertions(+), 9 deletions(-)