From patchwork Fri Jul 12 05:28:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168899 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395959ilk; Thu, 11 Jul 2019 22:30:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqxTy8pNWyD56scO12u8/HwcT9RmtJyIdTTsAaCwRTjZvIs9FnB7pzLohjhZbBZ65edHMsBP X-Received: by 2002:a17:90b:95:: with SMTP id bb21mr9542646pjb.8.1562909450970; Thu, 11 Jul 2019 22:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909450; cv=none; d=google.com; s=arc-20160816; b=LOrKnPI2cU0UzSrY+sZg8vfD1t7GvZzIAN+WcopLfElqZoZ2lagONAiE6jVf+pibPB GP3E4g61tkRJak/QJw8+ZAYQ8xxydVSnEiyxxAgMhOU/35lIGQFX9L2hyC021AgDXdjO frOt5cOfLAcla5B59+EbpLR2LAxAkQD5Q8f2OhUgcaLoWK3vH6iLMCdOMnkuwYuaKbyG a/tYv8m2XNNlBM0Hp6sLz+0+haDWmiD12WdPu1e35u0QYIjiMsC3u+JsSwkSNzEkFu3k zG2Cs3r7qcukm/RsppZHb8Vhx7rKd+IL2UpYH85I6YUtXztQIot8Pjm8tW0l0B64wQj1 0rBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=A46e7QixvIkQ11tJRIldlF/tIX6gtmkAoibvIS+88lQkguQebhBNu7N5iIv37zgpe0 B5cCp/iIDCiNng7YPJnVLUMH+OzqnsqATUMlCt9wd+tn3Gm9tcEJaeW3g0v7LXw2uxDn vSzti5JZllKIDUr0QZOlvpSLvDlKRIlSEpJQWrCnPnDmEBNe4hbxVwey8c0A+zIi24F3 8paxumfwIOP6UuRLcJsWwUotHlVIFW79v3TBI1r53KSsbJXWrVuWn9T2iTo9L8OV28nG q+zHdafoza4xaA71R0ZR4kcoErLAmjHOPpJr03OAwx2gZxdSh+PJFtp92+sMyUH6mJqo JzQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IB3JJQIu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.50; Thu, 11 Jul 2019 22:30:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IB3JJQIu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725939AbfGLFau (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:50 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:32820 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFau (ORCPT ); Fri, 12 Jul 2019 01:30:50 -0400 Received: by mail-pf1-f196.google.com with SMTP id g2so3805217pfq.0 for ; Thu, 11 Jul 2019 22:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=IB3JJQIuHZFizIZtXA/n0rZ+jWpJAoAWsj6UXhog4Cu3WwWA4r+1mzjeDP0UWlYyUU RFgL0SloPebXsJu8mt3U4ylWXkjD0MJNtbkYp9JE+8QRnpYTZP8ktiBEND77wvW48kDA mfANFSESMn2tuCqWkTeSZiRxstk71UyJPH9T37bM+5q6NhtpdUY6OPy3sLW/7DxsBZBn M3PpWUIWD06CMpTvCRIceM6rg/cDgGnBDL50UycxLRERqYJyaks0hMMG+rn2pM4q06ir d6GmHDoIntf3zGW150E8QhXpG8GxOvmvt2DA+7THz23z808tE2wLjSqM2eqlwTlRAh87 aBbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=bIC35pFh8TbVTaxqZGU6wqhMDsaEg5nEH+fuemXUcQQ1HRwqYnYca3lLTdstS2LPwg oVll+F5iN9kF3MMMhNcNaqFpNKIoXQc96dCx+VZ0PGy9DrJiJpUQ80JY4bWcWF8jbLWm 3zTyLDvQs1aJi1MDttKOatFs9eD0pjrtFMylZqJzd9fyRqOG7zW6/x/gthbUWqBpk18u Isge7rWT2kA1oFpQJEHtaCeZ+ylmJdzi+mxAS4z1tVhdIKve6xrgao4t812HSp9M7vzb pgwnilXMoUdydFOmwA7AsbOM5Ozgz9ThHz4wLRo7fbhux6dYJzIYk8/If1YJxsiPZuxH LjcQ== X-Gm-Message-State: APjAAAXtYAQlp/lczThPxNafaDBXFevHfmkVYm1r/I4jNfJHZP6Jbmgw rg0Hn/BesIURA7ON+XPoGU+uGT1m74M= X-Received: by 2002:a63:7455:: with SMTP id e21mr2804274pgn.439.1562909448746; Thu, 11 Jul 2019 22:30:48 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id u134sm6825242pfc.19.2019.07.11.22.30.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:48 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 40/43] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Date: Fri, 12 Jul 2019 10:58:28 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f2d3b2e8759a5833df6f022e42df2d581e6d843c upstream. One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 141 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4c45fd75db5d..60c2ad6316d8 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -122,5 +122,146 @@ asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a5, unsigned long a6, unsigned long a7, struct arm_smccc_res *res); +/* SMCCC v1.1 implementation madness follows */ +#ifdef CONFIG_ARM64 + +#define SMCCC_SMC_INST "smc #0" +#define SMCCC_HVC_INST "hvc #0" + +#elif defined(CONFIG_ARM) +#include +#include + +#define SMCCC_SMC_INST __SMC(0) +#define SMCCC_HVC_INST __HVC(0) + +#endif + +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(inst "\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if (___res) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while (0) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + */ +#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) + +/* + * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make HVC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the HVC instruction. The return values are updated with the content + * from register 0 to 3 on return from the HVC instruction if not NULL. + */ +#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) + #endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/