From patchwork Mon Feb 21 08:49:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 544997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21064C433EF for ; Mon, 21 Feb 2022 08:58:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346754AbiBUI7D (ORCPT ); Mon, 21 Feb 2022 03:59:03 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:60138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346751AbiBUI6c (ORCPT ); Mon, 21 Feb 2022 03:58:32 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E364723BED; Mon, 21 Feb 2022 00:54:43 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 17914B80EB6; Mon, 21 Feb 2022 08:54:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4CAE8C340E9; Mon, 21 Feb 2022 08:54:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1645433663; bh=bJzk+MFGzdcR9CO+eXnU6w55eP9b3igNabas5tmvae0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iLYQ61Ep9uojqROjgCeyeIfhekto8bef3Abkr5PdihS5Hek+Fdf5SDa0OeLPlNbDy txA0rMRtxF66Hoa2RysZG6C6gGNn3MtHNu/uSfr6PkXijD67yRHqBjazF5ozd5whXP c+erT5kJnbCpz1vbEktXqBL+d6OcsBA+1MzLPRhA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marc St-Amand , Harini Katakam , Nicolas Ferre , Conor Dooley , "David S. Miller" , Sasha Levin Subject: [PATCH 4.14 45/45] net: macb: Align the dma and coherent dma masks Date: Mon, 21 Feb 2022 09:49:36 +0100 Message-Id: <20220221084911.916299159@linuxfoundation.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220221084910.454824160@linuxfoundation.org> References: <20220221084910.454824160@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc St-Amand [ Upstream commit 37f7860602b5b2d99fc7465f6407f403f5941988 ] Single page and coherent memory blocks can use different DMA masks when the macb accesses physical memory directly. The kernel is clever enough to allocate pages that fit into the requested address width. When using the ARM SMMU, the DMA mask must be the same for single pages and big coherent memory blocks. Otherwise the translation tables turn into one big mess. [ 74.959909] macb ff0e0000.ethernet eth0: DMA bus error: HRESP not OK [ 74.959989] arm-smmu fd800000.smmu: Unhandled context fault: fsr=0x402, iova=0x3165687460, fsynr=0x20001, cbfrsynra=0x877, cb=1 [ 75.173939] macb ff0e0000.ethernet eth0: DMA bus error: HRESP not OK [ 75.173955] arm-smmu fd800000.smmu: Unhandled context fault: fsr=0x402, iova=0x3165687460, fsynr=0x20001, cbfrsynra=0x877, cb=1 Since using the same DMA mask does not hurt direct 1:1 physical memory mappings, this commit always aligns DMA and coherent masks. Signed-off-by: Marc St-Amand Signed-off-by: Harini Katakam Acked-by: Nicolas Ferre Tested-by: Conor Dooley Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/cadence/macb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index b07ea8a26c20a..045ab0ec5ca25 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -3528,7 +3528,7 @@ static int macb_probe(struct platform_device *pdev) #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) { - dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); bp->hw_dma_cap |= HW_DMA_CAP_64B; } #endif