From patchwork Sat Jun 5 23:47:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 455257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7DBFC48BC2 for ; Sun, 6 Jun 2021 00:32:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A697861415 for ; Sun, 6 Jun 2021 00:32:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbhFFAeM (ORCPT ); Sat, 5 Jun 2021 20:34:12 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:32982 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230108AbhFFAeM (ORCPT ); Sat, 5 Jun 2021 20:34:12 -0400 Message-Id: <20210606001323.213119142@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1622939542; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2VF+NDL8aHdPcXubNDnSyn1t+1GOHiiBi2fdFTg3nOM=; b=jiiyTGEKqvRF7f1KpsKdYkwiYL4Aal3GwsvEHPf1FjsQC7FKS2WNILCVOA+VHphUf6mmvw c3Jt9P5JWXNQ8nRXZp8ViJz6A6ZfYCIpdACQpiLURm3d0NOE2U4NvUxBLFWNHPb1AejRpq s3NnaGRmfLpDdSQLIkh1jXxKi+dHgbHOp4rkNZbo6fE8cU7cM4LGl8goY/k3CGpJzzhfww 7WSWjfd+pwKNbXFEgf8+KUDOq23sFEz6tOTQAtn3qWPxZv+bnh9QeXW+L7vzqDinNxbEM8 mk5q0JHS+yEgFMV8yOpJ+GOKom0QsZymfQIn8isjI8lOkU/apYl+hsC5ns8ceg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1622939542; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=2VF+NDL8aHdPcXubNDnSyn1t+1GOHiiBi2fdFTg3nOM=; b=AdKrueCoATMjJEwt8Hg+P15B3Q9oo77qvB98uiqKQ4eq/HD86VLeZFI2K/iH8nMdZtrz7a F0ZBCi2XRdXcgdAg== Date: Sun, 06 Jun 2021 01:47:45 +0200 From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Andy Lutomirski , Dave Hansen , Fenghua Yu , Tony Luck , Yu-cheng Yu , Sebastian Andrzej Siewior , stable@vger.kernel.org Subject: [patch V2 03/14] x86/fpu: Invalidate FPU state after a failed XRSTOR from a user buffer References: <20210605234742.712464974@linutronix.de> MIME-Version: 1.0 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Andy Lutomirski Both Intel and AMD consider it to be architecturally valid for XRSTOR to fail with #PF but nonetheless change the register state. The actual conditions under which this might occur are unclear [1], but it seems plausible that this might be triggered if one sibling thread unmaps a page and invalidates the shared TLB while another sibling thread is executing XRSTOR on the page in question. __fpu__restore_sig() can execute XRSTOR while the hardware registers are preserved on behalf of a different victim task (using the fpu_fpregs_owner_ctx mechanism), and, in theory, XRSTOR could fail but modify the registers. If this happens, then there is a window in which __fpu__restore_sig() could schedule out and the victim task could schedule back in without reloading its own FPU registers. This would result in part of the FPU state that __fpu__restore_sig() was attempting to load leaking into the victim task's user-visible state. Invalidate preserved FPU registers on XRSTOR failure to prevent this situation from corrupting any state. [1] Frequent readers of the errata lists might imagine "complex microarchitectural conditions" Fixes: 1d731e731c4c ("x86/fpu: Add a fastpath to __fpu__restore_sig()") Signed-off-by: Andy Lutomirski Signed-off-by: Thomas Gleixner Cc: stable@vger.kernel.org --- V2: Amend changelog - Borislav --- arch/x86/kernel/fpu/signal.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -369,6 +369,27 @@ static int __fpu__restore_sig(void __use fpregs_unlock(); return 0; } + + if (test_thread_flag(TIF_NEED_FPU_LOAD)) { + /* + * The FPU registers do not belong to current, and + * we just did an FPU restore operation, restricted + * to the user portion of the register file, and + * failed. In the event that the ucode was + * unfriendly and modified the registers at all, we + * need to make sure that we aren't corrupting an + * innocent non-current task's registers. + */ + __cpu_invalidate_fpregs_state(); + } else { + /* + * As above, we may have just clobbered current's + * user FPU state. We will either successfully + * load it or clear it below, so no action is + * required here. + */ + } + fpregs_unlock(); } else { /*