From patchwork Fri May 14 09:50:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 438826 Delivered-To: patch@linaro.org Received: by 2002:a02:b78d:0:0:0:0:0 with SMTP id f13csp183090jam; Fri, 14 May 2021 02:50:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4llouE0VmJrFfHd2T6DfYXfmcQ7KzJH6UQMA7rmuqo36oqF5yRSvdd68kvSOU/WMOAoV6 X-Received: by 2002:a05:6402:14c1:: with SMTP id f1mr12441539edx.334.1620985806633; Fri, 14 May 2021 02:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620985806; cv=none; d=google.com; s=arc-20160816; b=sIbCqT73rb6xhU0l8dANEDgAu6+T2OZuVoV6GLPui4Ylekc0AGPyB/LyVh66SSj5bM VLVNnrpE4QNMs7wOCPe7j9GrTwp3G7l+6yW9gdJEvmWUtuGT56AWnjCqOnh/KR4iNiJq vrntYVkd41fM1Nshsjot8nYbMjlmy8ftAGnaCRnArWpb1XKogK/nQX/SH/DZQVRwl5r2 KOqh0QrXL2SNOxPXXVCq8UQqIw8nzL6HwjEHdQwvpzQxGTnwebGWSzOXYKwO/uIkJ67w 5uLM1RtMx++vTgT4SqMUn48GtD+azFIWNB6Pg5uott13UjwiDus0hKZxuU3Q3VvVSuHT ZmCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=Pl6FW4vG3/wAJ8aQqkmsdlgj5BFZ6jlyyLo3J/1W1A0=; b=J9+yieTGXzTuAIs1QjYJzddQqzOm2G2qiGCIm79gLtlBvUVzQ5x0a5YShmUusY/2Aa sCfkjCgO0ujRi7azYJszOYeohNFNSaxCiKU0Fm7Hqlu5J1VcvLyu0I71N/zjAVaN5GHD nHfXDdj+bnMcW0dOYio79bhGy57c+RhWg6S0fJT1X8fRTwp+rZkrKYkZp6DdJHHEqxaC Wg8Ez37xAM1k/7HEPU5o0p3sw1Bj750KpYOxwcptCv9McX7kZTee97PJjzabs+WLiUFY 7wgO1X2D4lM9T+Bwh+Cpc5avKpXdHCFP1wtPydNoy6JtExXyReRA/3SD+hdSDqesma2e dU4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i2si6682414ejp.181.2021.05.14.02.50.06; Fri, 14 May 2021 02:50:06 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbhENJvQ (ORCPT + 12 others); Fri, 14 May 2021 05:51:16 -0400 Received: from mail.kernel.org ([198.145.29.99]:55906 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbhENJvP (ORCPT ); Fri, 14 May 2021 05:51:15 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A429D613B6; Fri, 14 May 2021 09:50:03 +0000 (UTC) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Cc: Mark Rutland , stable@vger.kernel.org, Will Deacon , Steven Price Subject: [PATCH] arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache() Date: Fri, 14 May 2021 10:50:01 +0100 Message-Id: <20210514095001.13236-1-catalin.marinas@arm.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org To ensure that instructions are observable in a new mapping, the arm64 set_pte_at() implementation cleans the D-cache and invalidates the I-cache to the PoU. As an optimisation, this is only done on executable mappings and the PG_dcache_clean page flag is set to avoid future cache maintenance on the same page. When two different processes map the same page (e.g. private executable file or shared mapping) there's a potential race on checking and setting PG_dcache_clean via set_pte_at() -> __sync_icache_dcache(). While on the fault paths the page is locked (PG_locked), mprotect() does not take the page lock. The result is that one process may see the PG_dcache_clean flag set but the I/D cache maintenance not yet performed. Avoid test_and_set_bit(PG_dcache_clean) in favour of separate test_bit() and set_bit(). In the rare event of a race, the cache maintenance is done twice. Signed-off-by: Catalin Marinas Cc: Cc: Will Deacon Cc: Steven Price --- Found while debating with Steven a similar race on PG_mte_tagged. For the latter we'll have to take a lock but hopefully in practice it will only happen when restoring from swap. Separate thread anyway. There's at least arch/arm with a similar race. Powerpc seems to do it properly with separate test/set. Other architectures have a bigger problem as they do a similar check in update_mmu_cache(), called after the pte was already exposed to user. I looked at fixing this in the mprotect() code but taking the page lock will slow it down, so not sure how popular this would be for such a rare race. arch/arm64/mm/flush.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Steven Price Acked-by: Will Deacon diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index ac485163a4a7..6d44c028d1c9 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -55,8 +55,10 @@ void __sync_icache_dcache(pte_t pte) { struct page *page = pte_page(pte); - if (!test_and_set_bit(PG_dcache_clean, &page->flags)) + if (!test_bit(PG_dcache_clean, &page->flags)) { sync_icache_aliases(page_address(page), page_size(page)); + set_bit(PG_dcache_clean, &page->flags); + } } EXPORT_SYMBOL_GPL(__sync_icache_dcache);