From patchwork Mon Apr 12 08:40:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 419518 Delivered-To: patch@linaro.org Received: by 2002:a02:c4d2:0:0:0:0:0 with SMTP id h18csp1566702jaj; Mon, 12 Apr 2021 02:08:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxGIFZQDg4pxWiIHlU27n7tL2cPOX1ABUHl6r6b7hNgDBcQON3MwIcfbJyYHQeE4WUqIuxV X-Received: by 2002:aa7:96bc:0:b029:1f6:9937:fe43 with SMTP id g28-20020aa796bc0000b02901f69937fe43mr24265087pfk.68.1618218522546; Mon, 12 Apr 2021 02:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618218522; cv=none; d=google.com; s=arc-20160816; b=dJ6ove6M35Rrzu/aSp6SED/nyhAT7Vm6oIicfVuPavDaEYEog3X9R6eF/AzSAHyXZy oLZk9myQ8YF5ZJlkln1jQjFoSevOEJojJIPbkM6i8e8phezpwffXTELn+Z6rNm5y98O9 II1c2T15U6xD3P1Q8I1qbS+RMoYkBjZQbnk9tv5+UDVjIAbI/4WhiTT04VVipqBPUIz5 o/ePMXbC8NKe3QbsnSR1Qyo0nNwM4X+9yKDO0Zatl8Zv7DICAfTJPz6tkrQeu7DTe1sc nJweAMKJ7kBI1I7xAoaONnFyCfR3LRuzOR0p8WZ3UweQ/CeEgNygF461ymh05e87Btdx 826Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tl+8ssDXK5uNqhm2XAn2XyD+fnBB5xOjREA2ADTW98Y=; b=f/4e5ZfTAsrQWuuY7L9Ds7g5z/cMLaXuQJo5g/7ZWLokQrX3kls3zO8M4BP10Fpm5H 1K35Uq7Q4XlYZcaqQ3ct82pVq6lT0DOBEzC+NAL6OaBx0Ln/YIa0O/7LjfMWh8puqVK3 VNFgamqpvZnL7yJ+5KUloV4tJnCkv9/L6M6i62+H049cYefJJ3xjQaI3f7rqGWOGunY0 3UdvGLAt3ScopCdGfb++iG2H4nXECh07tD0XWtf7UiviYKqxJCX79yYutvKl2P5iT9II NaxcjgZkD78r87PNLkHS4D0MXBqH/UFNy2cfulbH0k4LJlodNRKKwtmdnEvbbp/OuQab 7FWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=2r3vVGxF; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n22si13767521pjq.111.2021.04.12.02.08.42; Mon, 12 Apr 2021 02:08:42 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=2r3vVGxF; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239299AbhDLJI5 (ORCPT + 12 others); Mon, 12 Apr 2021 05:08:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:57182 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239210AbhDLJHA (ORCPT ); Mon, 12 Apr 2021 05:07:00 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9ED1F6139C; Mon, 12 Apr 2021 09:03:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1618218212; bh=3M81bUulRZ1OJ8K1jzIUjMAQrCb+nJsOaPN0EFVYXos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2r3vVGxF7nofdRGWqwaHSzQX8nOucWvWcw3dSWx2tbiRzWSX+lUM2OV5czAvLoCTa QuoNtMqvxPmQ3XPtYCOw+MhjaoO+r7ZwJCP7QpkvMfaZ3ldzfp3Gy5Z0XiHVe0I01O 2lKbOpAlbGMfQLyBIaEIbioKcfqgzhKK+NTbiyX0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Shengjiu Wang , Charles Keepax , Mark Brown , Sasha Levin Subject: [PATCH 5.11 113/210] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips Date: Mon, 12 Apr 2021 10:40:18 +0200 Message-Id: <20210412084019.773468969@linuxfoundation.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210412084016.009884719@linuxfoundation.org> References: <20210412084016.009884719@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Shengjiu Wang [ Upstream commit 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f ] The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz and sample rate is 44100Hz, with the configuration pllprescale=2, postscale=sysclkdiv=1, some chip may have wrong bclk and lrclk output with pll enabled in master mode, but with the configuration pllprescale=1, postscale=2, the output clock is correct. >From Datasheet, the PLL performs best when f2 is between 90MHz and 100MHz when the desired sysclk output is 11.2896MHz or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice. So search available sysclk_divs from 2 to 1 other than from 1 to 2. Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search") Signed-off-by: Shengjiu Wang Acked-by: Charles Keepax Link: https://lore.kernel.org/r/1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/wm8960.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 660ec46eecf2..ceaf3bbb18e6 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -707,7 +707,13 @@ int wm8960_configure_pll(struct snd_soc_component *component, int freq_in, best_freq_out = -EINVAL; *sysclk_idx = *dac_idx = *bclk_idx = -1; - for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { + /* + * From Datasheet, the PLL performs best when f2 is between + * 90MHz and 100MHz, the desired sysclk output is 11.2896MHz + * or 12.288MHz, then sysclkdiv = 2 is the best choice. + * So search sysclk_divs from 2 to 1 other than from 1 to 2. + */ + for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) { if (sysclk_divs[i] == -1) continue; for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {