From patchwork Mon Apr 12 08:40:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 419513 Delivered-To: patch@linaro.org Received: by 2002:a02:c4d2:0:0:0:0:0 with SMTP id h18csp1559920jaj; Mon, 12 Apr 2021 01:57:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7uKEDzsIaqspRbd5xCqPwg38OMG5jYRqaEWByf7wb1r87MxjMWXdQR1PKhSH3Hy3VzQR3 X-Received: by 2002:aa7:9516:0:b029:24c:c0:4fd2 with SMTP id b22-20020aa795160000b029024c00c04fd2mr5533785pfp.30.1618217870183; Mon, 12 Apr 2021 01:57:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618217870; cv=none; d=google.com; s=arc-20160816; b=KyWzhWTj10F5vHzrDeH0yyx+w3j9vbXd8zU1LeMF/KL8g9sI6fgjkX7svifyTVA0mC 9UnNnqWjN1FV6/rTvUQpyHxEkIis/GDsPq3dYHSY1rJHqt3AMrIihEqxiv9+td5Wg8ox ByaRpr/KRM23Ux7d2shYBVLBXTf44Fcl7qMziQ0CwD6m59t2mi/F/Ine1z1bTfGcoERw 1eUeGUzebLiHrF8mMdTnSAhbdPkRO5/VEE3uNT6lOmJSy5h1qGNfV4nFHEVRbpTlcZl/ AC9eu+dLAz0QxFrxaJ400D34SYo3PkjnVs8E33mScT8JKIiFjeqeEiSyTuKueBZ9mHm3 zW3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tl+8ssDXK5uNqhm2XAn2XyD+fnBB5xOjREA2ADTW98Y=; b=LeYla6kaMUlTGmXmQtwvBzZXwdpoRNW7PXu9TEuVl5pikdc2raukcX1Le1+CCqP2uf flwWAp5SF+OmRaYtqjS5D3gDoS92xVrMtjqN0b/MWia1bmHs/MTR167stx4Cu5H9+lCW itpljk4aBxGc4T7pAa7lGVC75Memr7pZ7nRsSJZWfoKZwqexBunlDs8rrpcd5a9JcYAC Yv8shLEzw1aQfOlFwtgaGBG/OXsgQiyLQLPQuOKaGK6AF/fPlQnIENcRRoH0Ir6AzygT PaEjGGJ94GPrZp5vJjEl/T5akfd8xSI+oBFGBlTIqktPriYdwZXLKonwD+lc8TkHqTTo a0OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=i79D2BNQ; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 36si6651292pgp.31.2021.04.12.01.57.49; Mon, 12 Apr 2021 01:57:50 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=i79D2BNQ; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238600AbhDLI6E (ORCPT + 12 others); Mon, 12 Apr 2021 04:58:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:49930 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238546AbhDLI42 (ORCPT ); Mon, 12 Apr 2021 04:56:28 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 445C461279; Mon, 12 Apr 2021 08:56:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1618217769; bh=3M81bUulRZ1OJ8K1jzIUjMAQrCb+nJsOaPN0EFVYXos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i79D2BNQO5MhVkkeuyzqcaIoU6wwDWbsIqJ1wXzdiImQ454WXKdeoFvAN8CWnMvIN XIL8wypSzwAO+XT+IPt0OlOJKaBfibI4ZU0xUT2YxwpiN1KjtWfcH1TO67mX7X8Yi+ 1TG1fd42Dlywfk+qhitlkkA8ui95MDpZ3NehJBjs= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Shengjiu Wang , Charles Keepax , Mark Brown , Sasha Levin Subject: [PATCH 5.10 103/188] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips Date: Mon, 12 Apr 2021 10:40:17 +0200 Message-Id: <20210412084017.077179484@linuxfoundation.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210412084013.643370347@linuxfoundation.org> References: <20210412084013.643370347@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Shengjiu Wang [ Upstream commit 16b82e75c15a7dbd564ea3654f3feb61df9e1e6f ] The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz and sample rate is 44100Hz, with the configuration pllprescale=2, postscale=sysclkdiv=1, some chip may have wrong bclk and lrclk output with pll enabled in master mode, but with the configuration pllprescale=1, postscale=2, the output clock is correct. >From Datasheet, the PLL performs best when f2 is between 90MHz and 100MHz when the desired sysclk output is 11.2896MHz or 12.288MHz, so sysclkdiv = 2 (f2/8) is the best choice. So search available sysclk_divs from 2 to 1 other than from 1 to 2. Fixes: 84fdc00d519f ("ASoC: codec: wm9860: Refactor PLL out freq search") Signed-off-by: Shengjiu Wang Acked-by: Charles Keepax Link: https://lore.kernel.org/r/1616150926-22892-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/wm8960.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 660ec46eecf2..ceaf3bbb18e6 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -707,7 +707,13 @@ int wm8960_configure_pll(struct snd_soc_component *component, int freq_in, best_freq_out = -EINVAL; *sysclk_idx = *dac_idx = *bclk_idx = -1; - for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { + /* + * From Datasheet, the PLL performs best when f2 is between + * 90MHz and 100MHz, the desired sysclk output is 11.2896MHz + * or 12.288MHz, then sysclkdiv = 2 is the best choice. + * So search sysclk_divs from 2 to 1 other than from 1 to 2. + */ + for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) { if (sysclk_divs[i] == -1) continue; for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {