From patchwork Mon Mar 29 07:57:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 410807 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp3427097jai; Mon, 29 Mar 2021 01:25:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkysMvyRKFmmKdIUSiB1Kq+51PWX6Fvq5Ao4mec8rrX9lTfJTm5H7AFQ46N5Kld/OZfMpt X-Received: by 2002:a17:906:6882:: with SMTP id n2mr27018271ejr.50.1617006300220; Mon, 29 Mar 2021 01:25:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617006300; cv=none; d=google.com; s=arc-20160816; b=dShhnYz8OqyovApB6JSKSU389uwkNrJg6DmcWR7/v7EER5ShXFIQ/IfAbnslrn2P89 2OtNBp2FAug8bPAPccusjzHbczqKizO0b+qpet8fL0op2pStmJNuwAFhuohgzJHMFnf2 LNYqG4wY/tDHpGG8xUmCuudR62DlZykqymWR1Z0if72c94ZJ+JOiaPQsLfL8ykCTSVEx kJxEi3f+0MwuaQ37BjWsiYo+/1ZcrPqstJRI9Z3+thMc0qjAgmuLr8sRSQBowJirIczw OQbwjpfXeqIPNjGEWiCRPcPJiObjmg+VKLA8iUuoP/g2qXf/Wia4YnS+r+WuNIVS3hoe 3Whg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MumCDK00qhBd6L/LbcWbPolQLA/o7IjJ3fJYzlcMoZU=; b=HlPtgki+U+Rqg4rVhQW2ezkvYAs0xwcogh4akFW8hNakoiW7WErMs31t60cZatE5/t JBG1588trPSXLpOrmoh6Hjs2bPzalL8nVZ3vf4GH+x3lzOHW+c96rZrUFCQjzAfuKP9O RTC4ZwSMZPIOpgrLBe75dc4LhAxV+OsqvaVF4de4Kvw3x9pQoeoYFLbv5RKSHgbhvy13 8HL4r9Le4BfZjCeztxupODl2g9usRfn5Qv6G/NE2HfdL1Sf6CsjGgPHK8KedfW4r+TKU 1J+tCLQTIy8Rzs/ekUdWFkvO/gRNB1NJj9g6/59BA3XyjXgv9710h9OqLllyYSv+FgGG Qwyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=NI6ongDA; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a3si10905631edr.505.2021.03.29.01.25.00; Mon, 29 Mar 2021 01:25:00 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=NI6ongDA; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233095AbhC2IYa (ORCPT + 12 others); Mon, 29 Mar 2021 04:24:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:40880 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233513AbhC2IXj (ORCPT ); Mon, 29 Mar 2021 04:23:39 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C21816044F; Mon, 29 Mar 2021 08:23:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1617006208; bh=RHIqCcF0DTcyY7IN0URo8sQrH/fKoLvRgDD/wApvKZo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NI6ongDAmP+QOelX1PmSAAox/ODDhmDy4p0aUFSL2r/U1ISArXXzdFc9pFJEuvckF se+AIHb9594qaSpQr041BV0+hyNu7eQL0VnPcnWb8bvTv+8Wh9rx++MTyTMBum3onJ 9JhVpTXvK58He7ipNwNLgGa3u7gShDI/dxGL8QfI= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jonathan Marek , Dmitry Baryshkov , Rob Clark , Sasha Levin Subject: [PATCH 5.10 140/221] drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code Date: Mon, 29 Mar 2021 09:57:51 +0200 Message-Id: <20210329075633.846380275@linuxfoundation.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210329075629.172032742@linuxfoundation.org> References: <20210329075629.172032742@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Dmitry Baryshkov [ Upstream commit 3b24cdfc721a5f1098da22f9f68ff5f4a5efccc9 ] Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on sm8250). Current code checks for pll->type before it is set (as it is set in the msm_dsi_pll_init() after calling device-specific functions. Cc: Jonathan Marek Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Dmitry Baryshkov Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 2 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 6 ++++-- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 5 +++-- 3 files changed, 8 insertions(+), 5 deletions(-) -- 2.30.1 diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c index a45fe95aff49..3dc65877fa10 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c @@ -163,7 +163,7 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev, break; case MSM_DSI_PHY_7NM: case MSM_DSI_PHY_7NM_V4_1: - pll = msm_dsi_pll_7nm_init(pdev, id); + pll = msm_dsi_pll_7nm_init(pdev, type, id); break; default: pll = ERR_PTR(-ENXIO); diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h index 3405982a092c..bbecb1de5678 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h @@ -117,10 +117,12 @@ msm_dsi_pll_10nm_init(struct platform_device *pdev, int id) } #endif #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id); +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id); #else static inline struct msm_dsi_pll * -msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) +msm_dsi_pll_7nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) { return ERR_PTR(-ENODEV); } diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c index 93bf142e4a4e..c1f6708367ae 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c @@ -852,7 +852,8 @@ err_base_clk_hw: return ret; } -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, + enum msm_dsi_phy_type type, int id) { struct dsi_pll_7nm *pll_7nm; struct msm_dsi_pll *pll; @@ -885,7 +886,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id) pll = &pll_7nm->base; pll->min_rate = 1000000000UL; pll->max_rate = 3500000000UL; - if (pll->type == MSM_DSI_PHY_7NM_V4_1) { + if (type == MSM_DSI_PHY_7NM_V4_1) { pll->min_rate = 600000000UL; pll->max_rate = (unsigned long)5000000000ULL; /* workaround for max rate overflowing on 32-bit builds: */