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[24.79.253.190]) by smtp.gmail.com with ESMTPSA id m4sm17131511pfa.53.2021.01.31.23.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 23:31:14 -0800 (PST) From: jassisinghbrar@gmail.com To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, Masahisa Kojima , Jassi Brar , stable@vger.kernel.org Subject: [PATCH] spi: spi-synquacer: fix set_cs handling Date: Mon, 1 Feb 2021 01:31:09 -0600 Message-Id: <20210201073109.9036-1-jassisinghbrar@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Masahisa Kojima When the slave chip select is deasserted, DMSTOP bit must be set. Fixes: b0823ee35cf9 ("spi: Add spi driver for Socionext SynQuacer platform") Signed-off-by: Masahisa Kojima Signed-off-by: Jassi Brar Cc: stable@vger.kernel.org --- drivers/spi/spi-synquacer.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1 diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 42e82dbe3d41..a3344f1cc8ff 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -490,6 +490,10 @@ static void synquacer_spi_set_cs(struct spi_device *spi, bool enable) val &= ~(SYNQUACER_HSSPI_DMPSEL_CS_MASK << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT); val |= spi->chip_select << SYNQUACER_HSSPI_DMPSEL_CS_SHIFT; + + if (!enable) + val |= SYNQUACER_HSSPI_DMSTOP_STOP; + writel(val, sspi->regs + SYNQUACER_HSSPI_REG_DMSTART); }