From patchwork Mon Oct 5 15:26:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 290619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 459C7C4363A for ; Mon, 5 Oct 2020 15:36:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 085AB2075A for ; Mon, 5 Oct 2020 15:36:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601912195; bh=MCQz+KguEDfWxlQPuiO4MegJXlw2ki31Y4guoRQTfwY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=jQbRwsiVbnpUfUayVfJkz7HABo+4dTOob6FhTz5pNuh6rXexaWzG5hgSYWOzd7Bu1 z5y2ZW4Ub+1HOBoaq5BzzGaXaJL6UZvv5Ue0cDJWJZqFeOHM48aOKN0aAuvAgzVo7F GFnIQ9F3bV9jvniccXb+uE4GFnafa8TY0oWqcYX4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728450AbgJEPgd (ORCPT ); Mon, 5 Oct 2020 11:36:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:60134 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728033AbgJEPce (ORCPT ); Mon, 5 Oct 2020 11:32:34 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 61273206DD; Mon, 5 Oct 2020 15:32:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601911952; bh=MCQz+KguEDfWxlQPuiO4MegJXlw2ki31Y4guoRQTfwY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=v30U4FpeyqFqx1AdVlEodzLcXi2xkE0VfypXjTaY++yjliaydMdXKlb02ut5vobJ8 AtjvOCQK6DbVtBkTvC25kaB5/vvB1C/2nFrALaLhQ8mvVBIoU2ialMOYW2FdWPfTD/ deZH+hH5E7AMmVIQYS2I3Dam4B8WaQNTR4WET9fU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marek Szyprowski , Lukasz Luba , Krzysztof Kozlowski , Sylwester Nawrocki Subject: [PATCH 5.8 13/85] clk: samsung: Keep top BPLL mux on Exynos542x enabled Date: Mon, 5 Oct 2020 17:26:09 +0200 Message-Id: <20201005142115.370229476@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201005142114.732094228@linuxfoundation.org> References: <20201005142114.732094228@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marek Szyprowski commit 0212a0483b0a36cc94cfab882b3edbb41fcfe1cd upstream. BPLL clock must not be disabled because it is needed for proper DRAM operation. This is normally handled by respective memory devfreq driver, but when that driver is not yet probed or its probe has been deferred the clock might get disabled what causes board hang. Fix this by calling clk_prepare_enable() directly from the clock provider driver. Cc: stable@vger.kernel.org Signed-off-by: Marek Szyprowski Reviewed-by: Lukasz Luba Tested-by: Lukasz Luba Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Sylwester Nawrocki Signed-off-by: Greg Kroah-Hartman --- drivers/clk/samsung/clk-exynos5420.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(str * main G3D clock enablement status. */ clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + /* + * Keep top BPLL mux enabled permanently to ensure that DRAM operates + * properly. + */ + clk_prepare_enable(__clk_lookup("mout_bpll")); samsung_clk_of_add_provider(np, ctx); }