From patchwork Tue Sep 29 10:59:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 291004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DFEC4727F for ; Tue, 29 Sep 2020 11:59:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 79E2A206CA for ; Tue, 29 Sep 2020 11:59:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601380745; bh=Kn9WjV9upfVvnTTOxznfqCRK8sRSDxv/X8OhWVQV4G4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=AJjZP+gIDJQdHXvuFsu/zQtaFxlUqmSI4SWpXnbGjTJOTUrcjPYjml4lodTmnTQYZ YC9eDNPnWwe2uVIWv2Bw73MqJl1YbHj7VZpICYm376VfFV6g8pi4lsvTLdijoJd676 Cig3keboAwrbP+1L54ViqE2NqPiK4vanydPaaR2c= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730546AbgI2L6q (ORCPT ); Tue, 29 Sep 2020 07:58:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:38692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730661AbgI2Lls (ORCPT ); Tue, 29 Sep 2020 07:41:48 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1118E206DB; Tue, 29 Sep 2020 11:41:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601379707; bh=Kn9WjV9upfVvnTTOxznfqCRK8sRSDxv/X8OhWVQV4G4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=loOmlsoSw1SgXNJZy+gaeetx8GSWZFsgRE9dJr/3knBTDAT+22uOk70hXBTq5PN9u ggC9jiTbwFCaevoJSWq1gl9c37PqAeic3x90Y03+rOn9gtZ5DGJ0KF2fKIVVxwNlcZ +OReSVdzuBg7mSfRAZ79OfRHdOr8uvAn4FdSRDpI= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jonathan Bakker , Kishon Vijay Abraham I , Sasha Levin Subject: [PATCH 5.4 253/388] phy: samsung: s5pv210-usb2: Add delay after reset Date: Tue, 29 Sep 2020 12:59:44 +0200 Message-Id: <20200929110022.722350239@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929110010.467764689@linuxfoundation.org> References: <20200929110010.467764689@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jonathan Bakker [ Upstream commit 05942b8c36c7eb5d3fc5e375d4b0d0c49562e85d ] The USB phy takes some time to reset, so make sure we give it to it. The delay length was taken from the 4x12 phy driver. This manifested in issues with the DWC2 driver since commit fe369e1826b3 ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.") where the endianness check would read the DWC ID as 0 due to the phy still resetting, resulting in the wrong endian mode being chosen. Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin --- drivers/phy/samsung/phy-s5pv210-usb2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/samsung/phy-s5pv210-usb2.c b/drivers/phy/samsung/phy-s5pv210-usb2.c index 56a5083fe6f94..32be62e498047 100644 --- a/drivers/phy/samsung/phy-s5pv210-usb2.c +++ b/drivers/phy/samsung/phy-s5pv210-usb2.c @@ -139,6 +139,10 @@ static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) udelay(10); rst &= ~rstbits; writel(rst, drv->reg_phy + S5PV210_UPHYRST); + /* The following delay is necessary for the reset sequence to be + * completed + */ + udelay(80); } else { pwr = readl(drv->reg_phy + S5PV210_UPHYPWR); pwr |= phypwr;