From patchwork Tue Sep 29 10:59:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 262886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46D8AC4727F for ; Tue, 29 Sep 2020 12:44:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ECB952064E for ; Tue, 29 Sep 2020 12:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601383470; bh=7ijBAKzbzL0P/b4iOpJn8EUDsQXKg0GqQ7+MvRna7d4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=uEisL6KL7K6IBXymxWcDIUHamzkJdU8e3IlHPWViCdK2eVK6vGQDQaEinF5CiEMVu s+IjEhe9/Xih+ealiBRjFlBdIsuFd/cEv5OEWZepzR7lKJhOXTfAeaEU4T+89e0AtM fWr+bfEHaGHDWH2Wsc51BgL19Nu5jggB1e+vDylU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729406AbgI2MoR (ORCPT ); Tue, 29 Sep 2020 08:44:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:47394 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728501AbgI2LIe (ORCPT ); Tue, 29 Sep 2020 07:08:34 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 72A4B21941; Tue, 29 Sep 2020 11:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601377706; bh=7ijBAKzbzL0P/b4iOpJn8EUDsQXKg0GqQ7+MvRna7d4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aWdSlcV7wB31/zdCH6bUAEsSWGDZjtYuwcTtPfDVoSkjIGW559hJ2M8cESFgk2DMq C3UDDcEVRtAZQYfDmH2zHyUHbvvFhSzaTZ59sl8rTqI22h20/f50CljiQtAi6lVHfo uGUqTiJsDS/g5pqO6tn0xcNVN4Z6nMcxSS0QyQ0o= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Mohan Kumar , Viswanath L , Takashi Iwai , Sasha Levin Subject: [PATCH 4.9 043/121] ALSA: hda: Clear RIRB status before reading WP Date: Tue, 29 Sep 2020 12:59:47 +0200 Message-Id: <20200929105932.326559547@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929105930.172747117@linuxfoundation.org> References: <20200929105930.172747117@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Mohan Kumar [ Upstream commit 6d011d5057ff88ee556c000ac6fe0be23bdfcd72 ] RIRB interrupt status getting cleared after the write pointer is read causes a race condition, where last response(s) into RIRB may remain unserviced by IRQ, eventually causing azx_rirb_get_response to fall back to polling mode. Clearing the RIRB interrupt status ahead of write pointer access ensures that this condition is avoided. Signed-off-by: Mohan Kumar Signed-off-by: Viswanath L Link: https://lore.kernel.org/r/1580983853-351-1-git-send-email-viswanathl@nvidia.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/hda/hda_controller.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index bd0e4710d15d7..79043b481d7b6 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -1158,16 +1158,23 @@ irqreturn_t azx_interrupt(int irq, void *dev_id) if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update)) active = true; - /* clear rirb int */ status = azx_readb(chip, RIRBSTS); if (status & RIRB_INT_MASK) { + /* + * Clearing the interrupt status here ensures that no + * interrupt gets masked after the RIRB wp is read in + * snd_hdac_bus_update_rirb. This avoids a possible + * race condition where codec response in RIRB may + * remain unserviced by IRQ, eventually falling back + * to polling mode in azx_rirb_get_response. + */ + azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); active = true; if (status & RIRB_INT_RESPONSE) { if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) udelay(80); snd_hdac_bus_update_rirb(bus); } - azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); } } while (active && ++repeat < 10);