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Wed, 16 Sep 2020 14:36:40 -0500 From: Qingqing Zhuo To: CC: , , , , , , Wesley Chalmers , Subject: [PATCH 08/15] drm/amd/display: Increase timeout for DP Disable Date: Wed, 16 Sep 2020 15:36:28 -0400 Message-ID: <20200916193635.5169-9-qingqing.zhuo@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200916193635.5169-1-qingqing.zhuo@amd.com> References: <20200916193635.5169-1-qingqing.zhuo@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 222a51a3-2325-43df-2acb-08d85a77d676 X-MS-TrafficTypeDiagnostic: BN6PR12MB1250: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gWvzieSWO7o+Iqm+HwKUorNshQ5nj/ODZiKHpqxW7aHmvXJVJUDZ4vwLe7WLdOV7dUm1uyuhDNlmQJWD+ini5rNCqUyikhtej3i4mhkz3P5NqEpi+3nRkPRP7U6A306OZiaJ5IDmmbtmZYotKdEIjTrT+ALdelElnJ7hS98XvLAGaPUfZ867UpMkLFxgx+r6yvQaDsGPL1FWzWKJhnr9OprxXv2bKSLfPF2mY7Vqm9FDI7j19ON4OXf0gBoR3Uw956aq8cR3DGDdhF80hEbfLEP7QqjCxs7NX3gp/zPfifRxntITYuipbgrmKbSydjshfQfmlSLB052HyWh9ZxCk7Utqeh5Fq2yBFEFz6HcZUlTbHQJxq5oFTOuNy4n7oJJHBhN5L20Ov1Zgb/hgkPCwIg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SATLEXMB02.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39850400004)(46966005)(1076003)(47076004)(83380400001)(82740400003)(8936002)(2906002)(2616005)(54906003)(82310400003)(81166007)(316002)(6916009)(8676002)(356005)(36756003)(478600001)(86362001)(426003)(5660300002)(70206006)(70586007)(336012)(186003)(6666004)(44832011)(26005)(4326008); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2020 19:36:41.7642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 222a51a3-2325-43df-2acb-08d85a77d676 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB02.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1250 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Wesley Chalmers [WHY] When disabling DP video, the current REG_WAIT timeout of 50ms is too low for certain cases with very high VSYNC intervals. [HOW] Increase the timeout to 102ms, so that refresh rates as low as 10Hz can be handled properly. Signed-off-by: Wesley Chalmers Reviewed-by: Aric Cyr Acked-by: Qingqing Zhuo Cc: --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c index 9cf139be3f40..f70fcadf1ee5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c @@ -896,10 +896,10 @@ void enc1_stream_encoder_dp_blank( */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); /* Larger delay to wait until VBLANK - use max retry of - * 10us*5000=50ms. This covers 41.7ms of minimum 24 Hz mode + + * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + * a little more because we may not trust delay accuracy. */ - max_retries = DP_BLANK_MAX_RETRY * 250; + max_retries = DP_BLANK_MAX_RETRY * 501; /* disable DP stream */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);