From patchwork Tue Sep 15 14:13:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "gregkh@linuxfoundation.org" X-Patchwork-Id: 309564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1963C43461 for ; Wed, 16 Sep 2020 00:19:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE19720739 for ; Wed, 16 Sep 2020 00:19:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600215547; bh=Hw1X4RE33CTzK4sAiopuEovNVhAN4Phqjl630csa/VU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=BEfl1b8VyZlt/l4KXmkqS6tved4UayATPXP5h0AYHvWShSJtHXOkWHk2DzhAo5kH+ YZpbBRJHsQ4yVJO1DmtgqF26SBOtYa2PvCUodbxqBPqDSo3KviaNA7IUm7nYj0wm0h KBqaM5ZMqHhX7DK8mxFkRC8RaS9YOwdOmrFwONRA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727177AbgIPATB (ORCPT ); Tue, 15 Sep 2020 20:19:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:38170 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726884AbgIOOWR (ORCPT ); Tue, 15 Sep 2020 10:22:17 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 885FE22272; Tue, 15 Sep 2020 14:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600179456; bh=Hw1X4RE33CTzK4sAiopuEovNVhAN4Phqjl630csa/VU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uOSXVAXhAX5LaGy4jaSrXVypvXpoyaChxKkNy/0IB6UREcpIEByprdIBk/oFdFVl+ LghERBl7lQdV+sFODIoHJA1HpucjE/BFzMmiLrI5O0vjWQuZlmirwCjdOB9vKFAbqR 36aS24UyXLo4CkBTulEmzqocHan+8jpmueV3HAxk= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Sandeep Raghuraman , Alex Deucher , Sasha Levin Subject: [PATCH 4.19 37/78] drm/amdgpu: Fix bug in reporting voltage for CIK Date: Tue, 15 Sep 2020 16:13:02 +0200 Message-Id: <20200915140635.439028153@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200915140633.552502750@linuxfoundation.org> References: <20200915140633.552502750@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Sandeep Raghuraman [ Upstream commit d98299885c9ea140c1108545186593deba36c4ac ] On my R9 390, the voltage was reported as a constant 1000 mV. This was due to a bug in smu7_hwmgr.c, in the smu7_read_sensor() function, where some magic constants were used in a condition, to determine whether the voltage should be read from PLANE2_VID or PLANE1_VID. The VDDC mask was incorrectly used, instead of the VDDGFX mask. This patch changes the code to use the correct defined constants (and apply the correct bitshift), thus resulting in correct voltage reporting. Signed-off-by: Sandeep Raghuraman Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 219440bebd052..72c0a2ae2dd4f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -3566,7 +3566,8 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, case AMDGPU_PP_SENSOR_GPU_POWER: return smu7_get_gpu_power(hwmgr, (uint32_t *)value); case AMDGPU_PP_SENSOR_VDDGFX: - if ((data->vr_config & 0xff) == 0x2) + if ((data->vr_config & VRCONF_VDDGFX_MASK) == + (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT)) val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); else