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Peter Anvin" , Jiri Olsa , Mark Rutland , Michael Petlan , Namhyung Kim , LKML , x86 , stable@vger.kernel.org Subject: [PATCH v2 1/7] perf/amd/uncore: Set all slices and threads to restore perf stat -a behaviour Date: Tue, 8 Sep 2020 16:47:34 -0500 Message-Id: <20200908214740.18097-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200908214740.18097-1-kim.phillips@amd.com> References: <20200908214740.18097-1-kim.phillips@amd.com> X-ClientProxiedBy: SN4PR0601CA0018.namprd06.prod.outlook.com (2603:10b6:803:2f::28) To BN8PR12MB2946.namprd12.prod.outlook.com (2603:10b6:408:9d::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from fritz.amd.com (165.204.77.11) by SN4PR0601CA0018.namprd06.prod.outlook.com (2603:10b6:803:2f::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3348.16 via Frontend Transport; Tue, 8 Sep 2020 21:48:03 +0000 X-Mailer: git-send-email 2.27.0 X-Originating-IP: [165.204.77.11] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: b4758c04-e346-4f04-8eab-08d85440de3c X-MS-TrafficTypeDiagnostic: BN7PR12MB2593: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1227; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8DXGx59f6Q47vX2A7lq+2ztaK/FNjzbXmD0zEZhDpT+FDVSEkF7pgPLjETwG+RYuuWgKefgLdxlqc7ffJ/3u7+pbP1EDOFAYsHm6Z0U9vpm4XVBN+sSy7Negb4eCItBoNj3jS6s7Gn6uIsq0vfr0NB9rHrX90DEg62GdhYqjos064dHEHdmdPGAfuFqR+9/Na1vh36pGNlBl1z97euJa26KUrAo8vnqLsbY8AP5UGRv17u5LMxMZcaBDBfH4mcwfseioWE2gwTSfnNqnrscMhaAGDAdYd3/gvidYr/3wTNbkn2a6gk/pivkv84htHjwQ/r3Owt0ZEmqtB8XgSW2aDsZ6MzFif58V0jbUbKjuVU7km5xRtCFAxCtWiwa7tCbsjdgUkDtKZE1qGQcGKPw+RA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN8PR12MB2946.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(136003)(39860400002)(366004)(396003)(376002)(346002)(7696005)(52116002)(83380400001)(6486002)(44832011)(956004)(2616005)(86362001)(7416002)(478600001)(66476007)(66556008)(66946007)(186003)(26005)(8936002)(2906002)(4326008)(16526019)(8676002)(966005)(316002)(6666004)(36756003)(5660300002)(54906003)(110136005)(1076003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: B8i4oxyGizuzAjcALvdW4TiCTICCzWpMCkpxJD5l8l8wwEPg1uZb2Yhr5G0gpGWy4jB+H5azhzd56H/uWosnwUpyIBO8oNc0VpDNlGSdE+R7KqlmBeNs1dQ6fCIoCn+Jyk1lc4Q4M0CHHXjegUhaWThNN8qRmgf0/p6Ysizw6JPqCL8HkHpFnIxDvhU+KZwY+ZvdzUmUx+lW7rhm88MfkBaM022EYPFYN9FrzzCgCORQ4V6GG0t1nylWilYC2OJ7lwnxzLj/0Dky5aGXf3+Jc9X7sGnrWZnTIGvv80Hn6ICyfpAtIURFju17lyTNMKYbkSRe+Xpju6BeIBejt5jXvyjc4qAJ6bf7IOosLe33aqyIos7KfvsKm6AdMXSZEG4Vbegms73DP0f1N/SJ1fKTVNLFfeK/HKkI/3fk/B/8nGkFAvA/lZZ+20VwfVPkmtciHArfGEBlScjEbFYAQ1KWaac/T6kBcgPRLo9yDiTcsmGJlKgxw9KjeYdDorukd7Qs21HLR5LMN4Wrh0Ugu0LHYUjdm32QDJGii4j3+niLTtb04Dnu5Nd6yexJwdYG2+37byvqREvuVFMsOc44VWUM6wGoZeYwJjEYTD8YsSMM1N3JawnkVx0WvJshR62Fh4y75iXJ4gsraYJ0yPxo6KKISg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b4758c04-e346-4f04-8eab-08d85440de3c X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB2946.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2020 21:48:05.8134 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fRvWQN2lFx8MFQgqlrQ8NtVemvYG2614mMW+AqWSIa9I9YoDD07mrla4MFAJgAb75WhJjb3TFYH4bQ2wT8e9og== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2593 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Commit 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs") inadvertently changed the uncore driver's behaviour wrt perf tool invocations with or without a CPU list, specified with -C / --cpu=. Change the behaviour of the driver to assume the former all-cpu (-a) case, which is the more commonly desired default. This fixes '-a -A' invocations without explicit cpu lists (-C) to not count L3 events only on behalf of the first thread of the first core in the L3 domain. BEFORE: Activity performed by the first thread of the last core (CPU#43) in CPU#40's L3 domain is not reported by CPU#40: sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default ... CPU36 21,835 l3_request_g1.caching_l3_cache_accesses CPU40 87,066 l3_request_g1.caching_l3_cache_accesses CPU44 17,360 l3_request_g1.caching_l3_cache_accesses ... AFTER: The L3 domain activity is now reported by CPU#40: sudo perf stat -a -A -e l3_request_g1.caching_l3_cache_accesses taskset -c 43 perf bench mem memcpy -s 32mb -l 100 -f default ... CPU36 354,891 l3_request_g1.caching_l3_cache_accesses CPU40 1,780,870 l3_request_g1.caching_l3_cache_accesses CPU44 315,062 l3_request_g1.caching_l3_cache_accesses ... Signed-off-by: Kim Phillips Fixes: 2f217d58a8a0 ("perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs") Cc: Stephane Eranian Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Ingo Molnar Cc: Thomas Gleixner Cc: Borislav Petkov Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: "H. Peter Anvin" Cc: Jiri Olsa Cc: Mark Rutland Cc: Michael Petlan Cc: Namhyung Kim Cc: LKML Cc: x86 Cc: stable@vger.kernel.org --- v2: no changes. Original submission: https://lore.kernel.org/lkml/20200323233159.19601-1-kim.phillips@amd.com/ arch/x86/events/amd/uncore.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 76400c052b0e..e7e61c8b56bd 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -181,28 +181,16 @@ static void amd_uncore_del(struct perf_event *event, int flags) } /* - * Convert logical CPU number to L3 PMC Config ThreadMask format + * Return a full thread and slice mask until per-CPU is + * properly supported. */ -static u64 l3_thread_slice_mask(int cpu) +static u64 l3_thread_slice_mask(void) { - u64 thread_mask, core = topology_core_id(cpu); - unsigned int shift, thread = 0; + if (boot_cpu_data.x86 <= 0x18) + return AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK; - if (topology_smt_supported() && !topology_is_primary_thread(cpu)) - thread = 1; - - if (boot_cpu_data.x86 <= 0x18) { - shift = AMD64_L3_THREAD_SHIFT + 2 * (core % 4) + thread; - thread_mask = BIT_ULL(shift); - - return AMD64_L3_SLICE_MASK | thread_mask; - } - - core = (core << AMD64_L3_COREID_SHIFT) & AMD64_L3_COREID_MASK; - shift = AMD64_L3_THREAD_SHIFT + thread; - thread_mask = BIT_ULL(shift); - - return AMD64_L3_EN_ALL_SLICES | core | thread_mask; + return AMD64_L3_EN_ALL_SLICES | AMD64_L3_EN_ALL_CORES | + AMD64_L3_F19H_THREAD_MASK; } static int amd_uncore_event_init(struct perf_event *event) @@ -232,7 +220,7 @@ static int amd_uncore_event_init(struct perf_event *event) * For other events, the two fields do not affect the count. */ if (l3_mask && is_llc_event(event)) - hwc->config |= l3_thread_slice_mask(event->cpu); + hwc->config |= l3_thread_slice_mask(); uncore = event_to_amd_uncore(event); if (!uncore)