From patchwork Mon Aug 17 15:16:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 266239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89024C433E3 for ; Mon, 17 Aug 2020 18:14:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 628DA20738 for ; Mon, 17 Aug 2020 18:14:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597688097; bh=fGjbhm6ieFwl0Pv8oddzM6Pl+xjoXp9fYXB/Sx3ueCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=0Talfr/YmXLuT0oxb5ntFJVT89Om+KnT2yqSpvUs9mIpYPu8ia8LLv4QeGK+D7fH4 ++FhhfZLqAABmacfXtNA3M93a4Aeq2/aKq2eoAKGwOEEbvP5DwepVmkgWMJA7REQcU gCkY+LPh7aDnvdWGTHs8TWnIuewFZcjLkAQwP4Do= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390611AbgHQSOf (ORCPT ); Mon, 17 Aug 2020 14:14:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:54542 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388395AbgHQQG0 (ORCPT ); Mon, 17 Aug 2020 12:06:26 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E9D3120772; Mon, 17 Aug 2020 16:06:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597680386; bh=fGjbhm6ieFwl0Pv8oddzM6Pl+xjoXp9fYXB/Sx3ueCg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ap8bMSVFeBpo3seRfZT4NYrGTD7mU7L36TbBoQFCKhbplICN1I2Yw4gMnH+lyvqA6 GpBZZdF1OfzNokE92rfYzW+W3ysaym1pZ6iPFLlpOw9wGnRhNYvCgD8pNeXFE2ClG9 5OMBSnKjVOj6VnAhGB2v9haUKQKGLCxHiEpb7OB0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, "Aneesh Kumar K.V" , Madhavan Srinivasan , Michael Ellerman , Sasha Levin Subject: [PATCH 5.4 159/270] powerpc/perf: Fix missing is_sier_aviable() during build Date: Mon, 17 Aug 2020 17:16:00 +0200 Message-Id: <20200817143803.759991736@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200817143755.807583758@linuxfoundation.org> References: <20200817143755.807583758@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Madhavan Srinivasan [ Upstream commit 3c9450c053f88e525b2db1e6990cdf34d14e7696 ] Compilation error: arch/powerpc/perf/perf_regs.c:80:undefined reference to `.is_sier_available' Currently is_sier_available() is part of core-book3s.c, which is added to build based on CONFIG_PPC_PERF_CTRS. A config with CONFIG_PERF_EVENTS and without CONFIG_PPC_PERF_CTRS will have a build break because of missing is_sier_available(). In practice it only breaks when CONFIG_FSL_EMB_PERF_EVENT=n because that also guards the usage of is_sier_available(). That only happens with CONFIG_PPC_BOOK3E_64=y and CONFIG_FSL_SOC_BOOKE=n. Patch adds is_sier_available() in asm/perf_event.h to fix the build break for configs missing CONFIG_PPC_PERF_CTRS. Fixes: 333804dc3b7a ("powerpc/perf: Update perf_regs structure to include SIER") Reported-by: Aneesh Kumar K.V Signed-off-by: Madhavan Srinivasan [mpe: Add detail about CONFIG_FSL_SOC_BOOKE] Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20200614083604.302611-1-maddy@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/perf_event.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h index 7426d7a90e1e1..7aba3c7ea25cd 100644 --- a/arch/powerpc/include/asm/perf_event.h +++ b/arch/powerpc/include/asm/perf_event.h @@ -12,6 +12,8 @@ #ifdef CONFIG_PPC_PERF_CTRS #include +#else +static inline bool is_sier_available(void) { return false; } #endif #ifdef CONFIG_FSL_EMB_PERF_EVENT