From patchwork Mon Aug 17 15:18:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 266337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5092C433DF for ; Mon, 17 Aug 2020 17:37:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9CB172063A for ; Mon, 17 Aug 2020 17:37:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597685838; bh=vm0JTt6+eVIK/yRCTVuNoCfBLIqluknSd5JwM5Juwak=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=QPZ8NSyeyhpdeBgBXJq1KycVr3Vy3WkfqmBLG8VMOIPLFGpRdIFLWvhS0njIVeMrT WF5g8UZOVmqrUk8t+b6Uw3J991Kp43DgpF3MxuHEG5iQo6RpRbChCXsnFSbiMeMc8D PTBqR6tDpaB/Dy1/lSq31eyydxZjyS0oiBR7puHw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729520AbgHQRgd (ORCPT ); Mon, 17 Aug 2020 13:36:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:32874 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730275AbgHQQRe (ORCPT ); Mon, 17 Aug 2020 12:17:34 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E11DE22B47; Mon, 17 Aug 2020 16:17:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597681053; bh=vm0JTt6+eVIK/yRCTVuNoCfBLIqluknSd5JwM5Juwak=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OZVcX2y+LnlewSrRAfpOHqH/+mzeJU/6Cfg4SHbr+2M78XFagLBekBg+GZmumoDH3 JWDzfjVrEfyJW7KXMBrfIu2zvxQe0LA6rvrAZ6DdDF1jv/oW62K9ep8AjZ4dsBKFSw eq3cUcjFpiEWDG20dsUORnaTClHO3ljfLQXdErbA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Sivaprakash Murugesan , Miquel Raynal Subject: [PATCH 4.19 161/168] mtd: rawnand: qcom: avoid write to unavailable register Date: Mon, 17 Aug 2020 17:18:12 +0200 Message-Id: <20200817143741.711267229@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200817143733.692105228@linuxfoundation.org> References: <20200817143733.692105228@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Sivaprakash Murugesan commit 443440cc4a901af462239d286cd10721aa1c7dfc upstream. SFLASHC_BURST_CFG is only available on older ipq NAND platforms, this register has been removed when the NAND controller got implemented in the qpic controller. Avoid writing this register on devices which are based on qpic NAND controller. Fixes: dce84760b09f ("mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller") Cc: stable@vger.kernel.org Signed-off-by: Sivaprakash Murugesan Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/1591948696-16015-2-git-send-email-sivaprak@codeaurora.org Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/qcom_nandc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -466,11 +466,13 @@ struct qcom_nand_host { * among different NAND controllers. * @ecc_modes - ecc mode for NAND * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset */ struct qcom_nandc_props { u32 ecc_modes; bool is_bam; + bool is_qpic; u32 dev_cmd_reg_start; }; @@ -2766,7 +2768,8 @@ static int qcom_nandc_setup(struct qcom_ u32 nand_ctrl; /* kill onenand */ - nandc_write(nandc, SFLASHC_BURST_CFG, 0); + if (!nandc->props->is_qpic) + nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); @@ -3022,12 +3025,14 @@ static const struct qcom_nandc_props ipq static const struct qcom_nandc_props ipq4019_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x0, }; static const struct qcom_nandc_props ipq8074_nandc_props = { .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), .is_bam = true, + .is_qpic = true, .dev_cmd_reg_start = 0x7000, };