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Wed, 5 Aug 2020 12:41:00 -0500 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 5 Aug 2020 12:41:00 -0500 From: Qingqing Zhuo To: CC: , , , , , , Aric Cyr , Subject: [PATCH 2/9] drm/amd/display: Fix incorrect backlight register offset for DCN Date: Wed, 5 Aug 2020 13:40:51 -0400 Message-ID: <20200805174058.11736-3-qingqing.zhuo@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200805174058.11736-1-qingqing.zhuo@amd.com> References: <20200805174058.11736-1-qingqing.zhuo@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c82266e7-30e4-4eb9-6085-08d83966b91b X-MS-TrafficTypeDiagnostic: MN2PR12MB3839: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1388; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FCidDYyBGtHGZpJ1DMZJ3Vu7JQcQRhp0Ob9gAXY4MWzsoZbQp4H0nC4zasHDDsriFyQ1OMSGkoytog4145lbQA8PHJzy9pcj9DfJrViN7UtF87gvpNynpyNu9wBKFQ9e1LeJ9teRkGJwupm6j+fcnkP80KBkaRh5i6O4oHGtZ3sWAx65c8TB8RhpZV5ADp5Km2falGUAhJzWmO8Grh5uffc0b4XlqC5LoXQHG+gBn4+oIf8HBX+u7POQ67puNrMcL/yd+3C4odn4qr41kBDLzMWvssWfeSKSZCIh4nrnwDL0OxWuGshZ+supnGn02QO/5M/JAa/AWOJSMOd5nzU79WORFQESxURdP7k1Btkg7yyJ4E1/TghsQaemFVnWpuHyFvHyPkI9B6Vgv9PhIcCIzg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SATLEXMB01.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFTY:; SFS:(4636009)(39860400002)(376002)(136003)(346002)(396003)(46966005)(356005)(54906003)(1076003)(70586007)(70206006)(186003)(316002)(478600001)(81166007)(8936002)(47076004)(336012)(36756003)(26005)(4326008)(6916009)(2616005)(6666004)(82740400003)(83380400001)(2906002)(82310400002)(44832011)(5660300002)(8676002)(426003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2020 17:41:02.6312 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c82266e7-30e4-4eb9-6085-08d83966b91b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB01.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3839 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Aric Cyr [Why] Typo in backlight refactor inctroduced wrong register offset. [How] Change DCE to DCN register map for PWRSEQ_REF_DIV Cc: stable@vger.kernel.org Signed-off-by: Aric Cyr Reviewed-by: Ashley Thomas Acked-by: Qingqing Zhuo --- drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h index 70ec691e14d2..99c68ca9c7e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h @@ -49,7 +49,7 @@ #define DCN_PANEL_CNTL_REG_LIST()\ DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \ DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \ - DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ + DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ SR(BL_PWM_CNTL), \ SR(BL_PWM_CNTL2), \ SR(BL_PWM_PERIOD_CNTL), \