From patchwork Tue Jun 23 19:56:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 223469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 763E7C433DF for ; Tue, 23 Jun 2020 20:29:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BAA12064B for ; Tue, 23 Jun 2020 20:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592944165; bh=Lla2QzJHafDNwWtTdQCrScCxhDZhO0dkV+9Bo6qCOCk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=e9O3Bu8KJnp8HDIKAikeS/7/w0cFWS9NBWhyx6uPc9tCGbKZ4CpsOuVfWDhTLJIP+ xcEFnFCy8sPAT0g4Mfo1wPntJlIeyJHY6M+pNWR5Kh3ogPkVrILMfP1rNVE5ChOWUh XuNQiT2rX3TRiQsyyvTXd0n+7a2+pqa/M3xUvNcs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390742AbgFWU3Y (ORCPT ); Tue, 23 Jun 2020 16:29:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:49350 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390968AbgFWU3V (ORCPT ); Tue, 23 Jun 2020 16:29:21 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C541A206C3; Tue, 23 Jun 2020 20:29:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592944161; bh=Lla2QzJHafDNwWtTdQCrScCxhDZhO0dkV+9Bo6qCOCk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xxcQU01oCpr2A3RcMEvCkgZCyNqH+k1fK2+IMaWBlUF2o5VEFSi9b5516k2sNeBMX VJhefI+UnGzqoeaA72PFEEMkZGfIBJx4CygxMLCWtx1h5XCYL807QXN/qt92xiZ780 aGjG9XMRo2Hz5p42LtniLJ4jdhhvTeZ5Lqliw9io= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jon Hunter , Thierry Reding , Sasha Levin Subject: [PATCH 5.4 166/314] arm64: tegra: Fix ethernet phy-mode for Jetson Xavier Date: Tue, 23 Jun 2020 21:56:01 +0200 Message-Id: <20200623195346.801150538@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195338.770401005@linuxfoundation.org> References: <20200623195338.770401005@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jon Hunter [ Upstream commit bba25915b172c72f6fa635f091624d799e3c9cae ] The 'phy-mode' property is currently defined as 'rgmii' for Jetson Xavier. This indicates that the RGMII RX and TX delays are set by the MAC and the internal delays set by the PHY are not used. If the Marvell PHY driver is enabled, such that it is used and not the generic PHY, ethernet failures are seen (DHCP is failing to obtain an IP address) and this is caused because the Marvell PHY driver is disabling the internal RX and TX delays. For Jetson Xavier the internal PHY RX and TX delay should be used and so fix this by setting the 'phy-mode' to 'rgmii-id' and not 'rgmii'. Fixes: f89b58ce71a9 ("arm64: tegra: Add ethernet controller on Tegra194") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 02909a48dfcd9..7899759a12f80 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -32,7 +32,7 @@ phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; mdio { #address-cells = <1>;