From patchwork Tue Jun 23 19:53:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 191600 Delivered-To: patch@linaro.org Received: by 2002:a54:3249:0:0:0:0:0 with SMTP id g9csp1365883ecs; Tue, 23 Jun 2020 14:22:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzp5F4/quwOh8KEQL5s7dJCLIpSOCxVkV/FWuEekeg5WyC/Ni9dYMniMLtnqdl40ngnUUZB X-Received: by 2002:a17:906:d973:: with SMTP id rp19mr20832882ejb.475.1592947334521; Tue, 23 Jun 2020 14:22:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592947334; cv=none; d=google.com; s=arc-20160816; b=EzVjlD7rRNq/BWgSBYt+kF27G+AV9/4Z3cRlxkhPjLyA7J54/rdeqST+OR84mZcHul Swe/pcLYxMuuDXrK3weWRy6NpE2rxRwZ6CHTqX6dUkSotQhOlIlbqk4pYxQZ7ji2KmlW eDnaHpN3GxrGkmQe3l4O38oPNLlHggklkhZfTyRBA/eLXVJiskMGdjT9/AIXPvNBdqfx LbKJTUdlwVzFVmaR1qI2AuBNyrXeGKhpFDxig0eWqFOIKQAGMnz6Oo42RFvfXKPytA3U olY29fVzZ8XakceFDzDo60JfTWosXziJyGr0m4rgxLrfC7M7SOphuSGcN45HSCYh+xWv KcvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nejIPFxJxfc6+ubPZovzHQcTqqp/4MD9yixshC8iPlg=; b=k/7sss84pq6n7yVsUVlL8VFzpGEz/o6VjEG3i4VvVWB4EIxIyZg9JUWG7m4Nnyu6ax 12f+936xgtzGSQUK29g+NzE0UkfOeRukmk34iazGhfEEt9jaJqDVBw65z4SjJEHYqEdS nXHt3CB+VQRAZ8e7d3bnKQBtPolZA4BnOnM0G0jDURgJV7Jo32GVv1hsaIizFEVGojlJ b1MyuA1ppP6waU3ls/QuX6o8nJO6ptJ+S7ts2eyPIGKFvZlEiE7NOiaon3juIDOuDJrt Xg4g8K3PQoLUuH1na8ZauUEW3osGrt8/s45lv6C/wf1boUSsKf4FkX1f+K2d1Q26PgOA bdTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Wsmh7nVW; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id lj9si5625300ejb.507.2020.06.23.14.22.14; Tue, 23 Jun 2020 14:22:14 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=Wsmh7nVW; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390348AbgFWVWH (ORCPT + 15 others); Tue, 23 Jun 2020 17:22:07 -0400 Received: from mail.kernel.org ([198.145.29.99]:40324 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390166AbgFWUWZ (ORCPT ); Tue, 23 Jun 2020 16:22:25 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6C2052064B; Tue, 23 Jun 2020 20:22:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592943744; bh=Xmddb0PGgjMb8z3kGUQmrF98teyc8qCD/2QReoPrssc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wsmh7nVW0yFCGSV7/u4JEhl4G63LxUV9v5CrWdme5RKQYnxKlphFo+EmJAg2QByJy LmqcbwdJ3QkAOxXnlMZBlQ6WL7/Mzc33ZmkT7QJeN6945TnibkhFzukJNPvgF4RsZe 9qAxxeo7b7ztKmKqSmExea0ktuwnopGdvhU8LQW4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Georgi Djakov , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Bryan ODonoghue , Sasha Levin Subject: [PATCH 5.4 008/314] clk: qcom: msm8916: Fix the address location of pll->config_reg Date: Tue, 23 Jun 2020 21:53:23 +0200 Message-Id: <20200623195339.191328443@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195338.770401005@linuxfoundation.org> References: <20200623195338.770401005@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Bryan O'Donoghue [ Upstream commit f47ab3c2f5338828a67e89d5f688d2cef9605245 ] During the process of debugging a processor derived from the msm8916 which we found the new processor was not starting one of its PLLs. After tracing the addresses and writes that downstream was doing and comparing to upstream it became obvious that we were writing to a different register location than downstream when trying to configure the PLL. This error is also present in upstream msm8916. As an example clk-pll.c::clk_pll_recalc_rate wants to write to pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an example lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf 0x01823010 GCC_BIMC_PLL_USER_CTL 0x01823014 GCC_BIMC_PLL_CONFIG_CTL This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. This error is likely not apparent since the bootloader will already have initialized these PLLs. This patch corrects the location of config_reg from PLL_CONFIG_CTL to PLL_USER_CTL for all relevant PLLs on msm8916. Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov Cc: Andy Gross Cc: Bjorn Andersson Cc: Michael Turquette Cc: Stephen Boyd Signed-off-by: Bryan O'Donoghue Link: https://lkml.kernel.org/r/20200329124116.4185447-1-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/qcom/gcc-msm8916.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 4e329a7baf2ba..17e4a5a2a9fde 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -260,7 +260,7 @@ static struct clk_pll gpll0 = { .l_reg = 0x21004, .m_reg = 0x21008, .n_reg = 0x2100c, - .config_reg = 0x21014, + .config_reg = 0x21010, .mode_reg = 0x21000, .status_reg = 0x2101c, .status_bit = 17, @@ -287,7 +287,7 @@ static struct clk_pll gpll1 = { .l_reg = 0x20004, .m_reg = 0x20008, .n_reg = 0x2000c, - .config_reg = 0x20014, + .config_reg = 0x20010, .mode_reg = 0x20000, .status_reg = 0x2001c, .status_bit = 17, @@ -314,7 +314,7 @@ static struct clk_pll gpll2 = { .l_reg = 0x4a004, .m_reg = 0x4a008, .n_reg = 0x4a00c, - .config_reg = 0x4a014, + .config_reg = 0x4a010, .mode_reg = 0x4a000, .status_reg = 0x4a01c, .status_bit = 17, @@ -341,7 +341,7 @@ static struct clk_pll bimc_pll = { .l_reg = 0x23004, .m_reg = 0x23008, .n_reg = 0x2300c, - .config_reg = 0x23014, + .config_reg = 0x23010, .mode_reg = 0x23000, .status_reg = 0x2301c, .status_bit = 17,