From patchwork Tue Jun 23 19:56:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 223287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3661C433E0 for ; Tue, 23 Jun 2020 21:05:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9611F20663 for ; Tue, 23 Jun 2020 21:05:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592946348; bh=1o+X3ffWXT48Wy5t9hf4664gVUk/HoOpHYw07xkfb9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=vKx8s/vRSAQbfZcROM1db+Zd1w3/fGTUgCANXYkPyQ0i5pqF+kuaXVNIbbwRFmv7r dvOCjME54oLtLlLeVGW8ueDsgb79VH6NYU0JJBKeDZGG71yW267S/E+Vq79cZoSLt5 /BZS+/JyXcN6oucLP1YfSF289z8zf7ockyaGKYpU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391818AbgFWUgt (ORCPT ); Tue, 23 Jun 2020 16:36:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:60034 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391814AbgFWUgt (ORCPT ); Tue, 23 Jun 2020 16:36:49 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9EF7C21527; Tue, 23 Jun 2020 20:36:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592944609; bh=1o+X3ffWXT48Wy5t9hf4664gVUk/HoOpHYw07xkfb9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MQLB2R2Zl/M9Joosvp/spNQTxz3F83XbR7gCoGe0NYspapA7jpv9GqqSz/qi/FdSH INsgrmRaDh3PFj37QsLJuoMUe5eN4HWaLkTKQGBUMifRJbSrjt4Lr9Z/RgYOpAJKVS 77uT6JE/JfC0xwJ8ojfYKGtif0WKAvOs/gJ5jlPc= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Hulk Robot , Jason Yan , Geert Uytterhoeven , Sasha Levin Subject: [PATCH 4.19 055/206] pinctrl: rza1: Fix wrong array assignment of rza1l_swio_entries Date: Tue, 23 Jun 2020 21:56:23 +0200 Message-Id: <20200623195319.683595984@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195316.864547658@linuxfoundation.org> References: <20200623195316.864547658@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jason Yan [ Upstream commit 4b4e8e93eccc2abc4209fe226ec89e7fbe9f3c61 ] The rza1l_swio_entries referred to the wrong array rza1h_swio_pins, which was intended to be rza1l_swio_pins. So let's fix it. This is detected by the following gcc warning: drivers/pinctrl/pinctrl-rza1.c:401:35: warning: ‘rza1l_swio_pins’ defined but not used [-Wunused-const-variable=] static const struct rza1_swio_pin rza1l_swio_pins[] = { ^~~~~~~~~~~~~~~ Fixes: 039bc58e73b77723 ("pinctrl: rza1: Add support for RZ/A1L") Reported-by: Hulk Robot Signed-off-by: Jason Yan Link: https://lore.kernel.org/r/20200417111604.19143-1-yanaijie@huawei.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-rza1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index f76edf6645397..021c19eaf12d6 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -421,7 +421,7 @@ static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { }; static const struct rza1_swio_entry rza1l_swio_entries[] = { - [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, + [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, }; /* RZ/A1L (r7s72102x) pinmux flags table */