From patchwork Fri Jun 19 14:32:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 223975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02CF3C433DF for ; Fri, 19 Jun 2020 15:49:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CEB132158C for ; Fri, 19 Jun 2020 15:49:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592581763; bh=CHs8IERwuWU9CkOnkywO3FsEwPb/FZijDcZUOEVtpTU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=y0TNttTPsC/aos3+95evHJT5dmnDJRCv8RWxJhR0XLtdVGOb0kVy53va8In0DnbRZ naakoQdwZFqGt4xr7KIvG4dF/G6wXAnU7JHE9gqyEDi6d7/lS4g70iuax2Tshru5pk bilDwlg/iFHritSw9ZfbwvuohucG4w4M7GHMGzIo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404413AbgFSPtI (ORCPT ); Fri, 19 Jun 2020 11:49:08 -0400 Received: from mail.kernel.org ([198.145.29.99]:57012 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393382AbgFSPZP (ORCPT ); Fri, 19 Jun 2020 11:25:15 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ADC84217A0; Fri, 19 Jun 2020 15:25:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592580314; bh=CHs8IERwuWU9CkOnkywO3FsEwPb/FZijDcZUOEVtpTU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WlFpuIFFxBs48mGC5NCLPltOwLnYVW5Aohqw0TRjTudM5pjSb7YXzGaXF4Il4EunC VR8ArpxvB839PtFSzYmhyFgGxVQ9ADH9NOnapG9ahCEFTX4xbacp1Vt4ja/WFLK/y7 vU1trP5xvziytc7WbAvgF4aTn/2SQ7CPMaQD67gU= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Alexey Malahov , Serge Semin , Thomas Bogendoerfer , Paul Burton , Ralf Baechle , Arnd Bergmann , Rob Herring , devicetree@vger.kernel.org, Sasha Levin Subject: [PATCH 5.7 202/376] mips: MAAR: Use more precise address mask Date: Fri, 19 Jun 2020 16:32:00 +0200 Message-Id: <20200619141719.904184704@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619141710.350494719@linuxfoundation.org> References: <20200619141710.350494719@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Serge Semin [ Upstream commit bbb5946eb545fab8ad8f46bce8a803e1c0c39d47 ] Indeed according to the MIPS32 Privileged Resource Architecgture the MAAR pair register address field either takes [12:31] bits for non-XPA systems and [12:55] otherwise. In any case the current address mask is just wrong for 64-bit and 32-bits XPA chips. So lets extend it to 59-bits of physical address value. This shall cover the 64-bits architecture and systems with XPA enabled, and won't cause any problem for non-XPA 32-bit systems, since address values exceeding the architecture specific MAAR mask will be just truncated with setting zeros in the unsupported upper bits. Co-developed-by: Alexey Malahov Signed-off-by: Alexey Malahov Signed-off-by: Serge Semin Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/mipsregs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 796fe47cfd17..274c2bf0d4a1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -753,7 +753,7 @@ /* MAAR bit definitions */ #define MIPS_MAAR_VH (_U64CAST_(1) << 63) -#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) +#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12) #define MIPS_MAAR_ADDR_SHIFT 12 #define MIPS_MAAR_S (_ULCAST_(1) << 1) #define MIPS_MAAR_VL (_ULCAST_(1) << 0)