From patchwork Fri Jun 19 14:31:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 223717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 070EBC433E0 for ; Fri, 19 Jun 2020 16:37:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDAB32067D for ; Fri, 19 Jun 2020 16:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592584673; bh=Ry2Gvl2NlFAU5jeHevDQ8/IbKTHZLhmA91zmWIh+tFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=dT3zPx9F1WL2bEruSqR9Z0JlVCTixrDq9NMCvnU5xRcybjFRhy9W2oF7DT7utR4fr Ao2Mk0lXZoTUCiai3LrXirGIT7XT6A4vt7s1xfEsQrFWfLUYMxaqN8MLJjoiZrXr+b ODC1mIzH4G4rtAluYUfvgFyEvjkKcpakdgsSJpqg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389054AbgFSQhw (ORCPT ); Fri, 19 Jun 2020 12:37:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:40418 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388666AbgFSOsK (ORCPT ); Fri, 19 Jun 2020 10:48:10 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7E1DA21835; Fri, 19 Jun 2020 14:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592578091; bh=Ry2Gvl2NlFAU5jeHevDQ8/IbKTHZLhmA91zmWIh+tFo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F3/KB5yChYXFGehwCzIVVIaJtxucTuE6nHG3qBukLaGbCVvVUT4m4Bn6GfIjmtrV+ 84HrEKy3xjyx9CtoDuPvINhJErXXu0d6chyFcBn4i12NCRQ2++4X5+c/Hq1wYOLruv qgVMLDBoahHaByT6GHQKLqeoZXWF1GN7BG3am16U= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, James Morse , Marc Zyngier Subject: [PATCH 4.14 061/190] KVM: arm64: Make vcpu_cp1x() work on Big Endian hosts Date: Fri, 19 Jun 2020 16:31:46 +0200 Message-Id: <20200619141636.628274197@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619141633.446429600@linuxfoundation.org> References: <20200619141633.446429600@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 3204be4109ad681523e3461ce64454c79278450a upstream. AArch32 CP1x registers are overlayed on their AArch64 counterparts in the vcpu struct. This leads to an interesting problem as they are stored in their CPU-local format, and thus a CP1x register doesn't "hit" the lower 32bit portion of the AArch64 register on a BE host. To workaround this unfortunate situation, introduce a bias trick in the vcpu_cp1x() accessors which picks the correct half of the 64bit register. Cc: stable@vger.kernel.org Reported-by: James Morse Tested-by: James Morse Acked-by: James Morse Signed-off-by: Marc Zyngier Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/kvm_host.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -292,8 +292,10 @@ struct kvm_vcpu_arch { * CP14 and CP15 live in the same array, as they are backed by the * same system registers. */ -#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) -#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) +#define CPx_BIAS IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) + +#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) +#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r) ^ CPx_BIAS]) #ifdef CONFIG_CPU_BIG_ENDIAN #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))