From patchwork Fri Jun 19 14:32:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 223664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5302C433DF for ; Fri, 19 Jun 2020 16:46:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9107720732 for ; Fri, 19 Jun 2020 16:46:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592585167; bh=AoCJP4443lKj4hyl1GTi/yV8cWeVgsfTrVCN5IgjCE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=Z6+P3lcBBLYlbeVykHyxQCUSX3IAzuIEF7v07R39LNGLucAftF0TbPbhCsO+HlVbC F1pYAvPsC/OyLxDMDw1F/27VTHsG2S8+I+DByVeeG0qb769yUJFMamWDO7gZbOHaBr 0nPh8Ec+11elIyYEexxrgqi3a0Qzsbu7az4we32M= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387755AbgFSOlm (ORCPT ); Fri, 19 Jun 2020 10:41:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:60220 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387470AbgFSOlf (ORCPT ); Fri, 19 Jun 2020 10:41:35 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3FAF12070A; Fri, 19 Jun 2020 14:41:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592577695; bh=AoCJP4443lKj4hyl1GTi/yV8cWeVgsfTrVCN5IgjCE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Qw6JWJreidvE1Kd2g2GT0T08FxtpjbAVJOzUlEinGNu2xfkHrLkkLmmqEeBmXN8Bk 0ZgtYefhDHzmdpgFwaIF29L4Oyg7QKePQBsPn/ceNC5wX/5wbH3dlULfEf3oEveJM7 wuP95CKRKlVKrdea/uDACx1mt43eIry2axh5H5ro= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Chris Wilson , Andi Shyti Subject: [PATCH 4.9 051/128] agp/intel: Reinforce the barrier after GTT updates Date: Fri, 19 Jun 2020 16:32:25 +0200 Message-Id: <20200619141622.889134311@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200619141620.148019466@linuxfoundation.org> References: <20200619141620.148019466@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Chris Wilson commit f30d3ced9fafa03e4855508929b5b6334907f45e upstream. After changing the timing between GTT updates and execution on the GPU, we started seeing sporadic failures on Ironlake. These were narrowed down to being an insufficiently strong enough barrier/delay after updating the GTT and scheduling execution on the GPU. By forcing the uncached read, and adding the missing barrier for the singular insert_page (relocation paths), the sporadic failures go away. Fixes: 983d308cb8f6 ("agp/intel: Serialise after GTT updates") Fixes: 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE") Signed-off-by: Chris Wilson Acked-by: Andi Shyti Cc: stable@vger.kernel.org # v4.0+ Link: https://patchwork.freedesktop.org/patch/msgid/20200410083535.25464-1-chris@chris-wilson.co.uk Signed-off-by: Greg Kroah-Hartman --- drivers/char/agp/intel-gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -845,6 +845,7 @@ void intel_gtt_insert_page(dma_addr_t ad unsigned int flags) { intel_private.driver->write_entry(addr, pg, flags); + readl(intel_private.gtt + pg); if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } @@ -870,7 +871,7 @@ void intel_gtt_insert_sg_entries(struct j++; } } - wmb(); + readl(intel_private.gtt + j - 1); if (intel_private.driver->chipset_flush) intel_private.driver->chipset_flush(); } @@ -1104,6 +1105,7 @@ static void i9xx_cleanup(void) static void i9xx_chipset_flush(void) { + wmb(); if (intel_private.i9xx_flush_page) writel(1, intel_private.i9xx_flush_page); }