From patchwork Tue Jun 16 15:33:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 224320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81DF4C433DF for ; Tue, 16 Jun 2020 16:18:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 551F820882 for ; Tue, 16 Jun 2020 16:18:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592324293; bh=him64+DPIChEX82ZwANJeJdiaQwo04Fo1rdBgwYSfcI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ZefsAA3RLAUWRR0dapDM9xCVhsWbrdhvRjrVL6TZzw9N1Q5osXvk27DNfMaGoYOMp KZCkbWOQThhKol9erdK5gmEBr78Q+pwj/D4Ukdjp7NQgx6Jr24wtiSTP4935rYDYas W/D/zjNohhDNoU5eUERJAweFC75xramYW1kpKFMw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730778AbgFPQSG (ORCPT ); Tue, 16 Jun 2020 12:18:06 -0400 Received: from mail.kernel.org ([198.145.29.99]:50934 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730668AbgFPPi1 (ORCPT ); Tue, 16 Jun 2020 11:38:27 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7170D20C56; Tue, 16 Jun 2020 15:38:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592321907; bh=him64+DPIChEX82ZwANJeJdiaQwo04Fo1rdBgwYSfcI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2eSr7AdD+LBysO4R1urWlb9bkeu6tM1WRf0EgVgKz9ThOLVSKmzooad/vDy1YB7cC uIlwElV4tCFeZMibvtvut/qdhHQQ/ydYRhKInfFwzQI4/V6AE9jw9RrIUhBZ+ax0bu h+Y9afHY8xzbW9Cs5v+8U3zxuuyXvETvnQHigScs= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Stephane Eranian , Kan Liang , "Peter Zijlstra (Intel)" Subject: [PATCH 5.4 044/134] perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont Date: Tue, 16 Jun 2020 17:33:48 +0200 Message-Id: <20200616153102.900302318@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200616153100.633279950@linuxfoundation.org> References: <20200616153100.633279950@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Kan Liang commit 0813c40556fce1eeefb996e020cc5339e0b84137 upstream. The mask in the extra_regs for Intel Tremont need to be extended to allow more defined bits. "Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0; Fixes: 6daeb8737f8a ("perf/x86/intel: Add Tremont core PMU support") Reported-by: Stephane Eranian Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20200501125442.7030-1-kan.liang@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/events/intel/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -1892,8 +1892,8 @@ static __initconst const u64 tnt_hw_cach static struct extra_reg intel_tnt_extra_regs[] __read_mostly = { /* must define OFFCORE_RSP_X first, see intel_fixup_er() */ - INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffffff9fffull, RSP_0), - INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1), + INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0), + INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1), EVENT_EXTRA_END };