From patchwork Mon Jun 1 17:53:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 225131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61361C433E0 for ; Mon, 1 Jun 2020 17:58:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 30586207DA for ; Mon, 1 Jun 2020 17:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1591034305; bh=sndQWg3R5DaAv3cGcLylgkaOjHQwf9bj1vLnR95t198=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=WU4ytKqDGDsZ2bLx89B7U8wd7Qpn+RYizQrMALqaXMsyi9i96euduQ+B/9IUNKt47 KxeNuzhx33AbaLOVkmxzKHRpIu5bXiZ1TKpemoWy69mnGvZBu4dJa/P0CK42poQhnl E2A+oIAs3lpsd6B+6y1JPVUaAI/pQaxfCUD0kzKk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728386AbgFAR6X (ORCPT ); Mon, 1 Jun 2020 13:58:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:40230 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728576AbgFAR6W (ORCPT ); Mon, 1 Jun 2020 13:58:22 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B002420776; Mon, 1 Jun 2020 17:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1591034302; bh=sndQWg3R5DaAv3cGcLylgkaOjHQwf9bj1vLnR95t198=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fh5ArfV0/zvRZz897FPy/B1KzsBWFlcOjvGlJ8NeHwP1zPgAwV+ok/w9xrAPUx+xv m8xZwnHLLgvB46/10gfYbsV/8Ghv5WOcVzrfizqDKvQJhCHIuDoudlB05P3S2nF9sm FWOXWSkUethufbXrfZQmAVFZcIsmLYEffPi4tqE0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Martyn Welch , Romain Perier , Fabio Estevam , Shawn Guo , Sasha Levin Subject: [PATCH 4.9 31/61] ARM: dts: imx: Correct B850v3 clock assignment Date: Mon, 1 Jun 2020 19:53:38 +0200 Message-Id: <20200601174017.555295599@linuxfoundation.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200601174010.316778377@linuxfoundation.org> References: <20200601174010.316778377@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Martyn Welch [ Upstream commit 1d0c7bb20c083a6e810d2142545b5606f8131080 ] The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m to avoid stepping on the LVDS output's toes, as the PLL can't be clocked to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the same time. As we are using ipu1_di0 and ipu2_di0, ensure both are switched to to pll2_pfd2_396m to avoid issues. The LDB driver will switch the required IPU to ldb_di1 when it uses it to drive LVDS. Signed-off-by: Martyn Welch Signed-off-by: Romain Perier Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6q-b850v3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 167f7446722a..e5e9a16155d9 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -57,7 +57,7 @@ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,