From patchwork Fri May 8 12:34:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 226144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48BEAC47254 for ; Fri, 8 May 2020 13:13:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E48224999 for ; Fri, 8 May 2020 13:13:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588943601; bh=1tUFM6fNGiDqtCHQbKjTGwJSyZBHktSvZBFVdBsQkYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=qHPEPbUP8EWuxjkhVJ/MhUPz4YqTAfXvtiibNWtuFlwfb9TQ+j+HjX1bpakF8n5uM NZQ+Cmco7n3uxPF3l41vLzVSPReFB+yVGyJdc61ahDk0Umcbhrj0YlusP11lgetvpQ vZOGzburE9mGTzOyf8i7m6ZR+4wer4n2Q2333S+4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729621AbgEHMsB (ORCPT ); Fri, 8 May 2020 08:48:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:51062 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729602AbgEHMr5 (ORCPT ); Fri, 8 May 2020 08:47:57 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E73F6221F7; Fri, 8 May 2020 12:47:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1588942076; bh=1tUFM6fNGiDqtCHQbKjTGwJSyZBHktSvZBFVdBsQkYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kh3QMsNop0zc3b4+YFrYG23DvWZJYPryeCwxNG014yHzaywwV54y8GUExBJ3aUC2Z 8VbMomP0CJJXshX2aLEK0Lw1h1GzNBuxOOAT8ZtxNz1IWccDgL/pcfxf9HoJmHvPd7 KHv4BE35xfn78EiwtHtHICSMT0x0NUTggbh9WkkE= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Cyrille Pitchen , Nicolas Ferre , "David S. Miller" Subject: [PATCH 4.4 288/312] net: macb: replace macb_writel() call by queue_writel() to update queue ISR Date: Fri, 8 May 2020 14:34:39 +0200 Message-Id: <20200508123144.643175909@linuxfoundation.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200508123124.574959822@linuxfoundation.org> References: <20200508123124.574959822@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Cyrille Pitchen commit ba5049945421b8d2f3e2af786a15d13b82316503 upstream. macb_interrupt() should not use macb_writel(bp, ISR, ) but only queue_writel(queue, ISR, ). There is one IRQ and one set of {ISR, IER, IDR, IMR} [1] registers per queue on gem hardware, though only queue0 is actually used for now to receive frames: other queues can already be used to transmit frames. The queue_readl() and queue_writel() helper macros are designed to access the relevant IRQ registers. [1] ISR: Interrupt Status Register IER: Interrupt Enable Register IDR: Interrupt Disable Register IMR: Interrupt Mask Register Signed-off-by: Cyrille Pitchen Fixes: bfbb92c44670 ("net: macb: Handle the RXUBR interrupt on all devices") Acked-by: Nicolas Ferre Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/cadence/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1104,7 +1104,7 @@ static irqreturn_t macb_interrupt(int ir macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) - macb_writel(bp, ISR, MACB_BIT(RXUBR)); + queue_writel(queue, ISR, MACB_BIT(RXUBR)); } if (status & MACB_BIT(ISR_ROVR)) {