From patchwork Wed Apr 22 09:55:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 227007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BF11C5518A for ; Wed, 22 Apr 2020 11:03:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 315D32076E for ; Wed, 22 Apr 2020 11:03:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587553400; bh=uHfJDHSXVBlydjhYSgY2opUgFgAkXRYmYj1mXLjkKrM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=yF+IExC6YwMFsYa8nBHWPNSX1Kp0utqhl2CdgvuKC86OucSHBfPfpjAIaOzvVqbNY obRuLGpEOx+dWpC+cJA75lWOf00DV0GNuyb/t5+evqepcjnMtpOIYPyPrMhEQL93nK THi9BwN3EKmBbUXBshsYoyDmtwd0yd2RqYlkjYHI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726584AbgDVJ76 (ORCPT ); Wed, 22 Apr 2020 05:59:58 -0400 Received: from mail.kernel.org ([198.145.29.99]:46790 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726575AbgDVJ7z (ORCPT ); Wed, 22 Apr 2020 05:59:55 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4B9B920776; Wed, 22 Apr 2020 09:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587549594; bh=uHfJDHSXVBlydjhYSgY2opUgFgAkXRYmYj1mXLjkKrM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UmKD59y79S0mPzQOFcK/t3orv1WKB/j1xN8CSIzvwWcZ7DYqSjJbHVCTBNpHT94JR 0zYBRNmtjaA3AHMHAPzpWIfm9e8Hc+AyBzSJbqzuRDC7JI5SPut5lrGjIeNx60hua3 pnry1aSWh7Oc5GDuaKRVErC2duq7YXyuYIMWXJgw= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Sungbo Eo , Marc Zyngier , Linus Walleij Subject: [PATCH 4.4 028/100] irqchip/versatile-fpga: Apply clear-mask earlier Date: Wed, 22 Apr 2020 11:55:58 +0200 Message-Id: <20200422095027.905688275@linuxfoundation.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200422095022.476101261@linuxfoundation.org> References: <20200422095022.476101261@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Sungbo Eo commit 6a214a28132f19ace3d835a6d8f6422ec80ad200 upstream. Clear its own IRQs before the parent IRQ get enabled, so that the remaining IRQs do not accidentally interrupt the parent IRQ controller. This patch also fixes a reboot bug on OX820 SoC, where the remaining rps-timer IRQ raises a GIC interrupt that is left pending. After that, the rps-timer IRQ is cleared during driver initialization, and there's no IRQ left in rps-irq when local_irq_enable() is called, which evokes an error message "unexpected IRQ trap". Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT") Signed-off-by: Sungbo Eo Signed-off-by: Marc Zyngier Reviewed-by: Linus Walleij Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200321133842.2408823-1-mans0n@gorani.run Signed-off-by: Greg Kroah-Hartman --- drivers/irqchip/irq-versatile-fpga.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -211,6 +211,9 @@ int __init fpga_irq_of_init(struct devic if (of_property_read_u32(node, "valid-mask", &valid_mask)) valid_mask = 0; + writel(clear_mask, base + IRQ_ENABLE_CLEAR); + writel(clear_mask, base + FIQ_ENABLE_CLEAR); + /* Some chips are cascaded from a parent IRQ */ parent_irq = irq_of_parse_and_map(node, 0); if (!parent_irq) { @@ -225,9 +228,6 @@ int __init fpga_irq_of_init(struct devic fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); #endif - writel(clear_mask, base + IRQ_ENABLE_CLEAR); - writel(clear_mask, base + FIQ_ENABLE_CLEAR); - /* * On Versatile AB/PB, some secondary interrupts have a direct * pass-thru to the primary controller for IRQs 20 and 22-31 which need