From patchwork Tue Mar 10 12:37:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 229492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53A28C18E5B for ; Tue, 10 Mar 2020 13:30:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2201624680 for ; Tue, 10 Mar 2020 13:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583847018; bh=5KKM57E/6i1ezCg+qBrkEvzBJzmv+cHuBS7GbTFfXtc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=HUfexZ9QtVsl8WMmbhPFJXAbdQc4YMpT+uteSL0krZJUyvxTOVYI+k9OkLAcM5vkx PwvbZKEdVi/Iq1iAS0MY0mh/eBoCKxsv7rI4X4Bqz45jzy9fnLFFEARHYy852SC/qJ 5ZLHa0yl+lxTuPEW5iPx2/d+7fYFes37eM8lUhN8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728684AbgCJMul (ORCPT ); Tue, 10 Mar 2020 08:50:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:55496 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728674AbgCJMul (ORCPT ); Tue, 10 Mar 2020 08:50:41 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BB82B24694; Tue, 10 Mar 2020 12:50:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1583844640; bh=5KKM57E/6i1ezCg+qBrkEvzBJzmv+cHuBS7GbTFfXtc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BPl9hmj15qlGXcvkIhWGFrLPQ6Ehl37aXLWo/47iNBB6ATDcwsrDYkvpVJ1V/6/Gm siyMpmFOmiuhIJEPhvjp/MRwobDafwc16YyF2/jZI/dsNw5UWWxfe1o1JeItiwZUkz m1VfBn+LhHOOj9c5j34+Km+0HTAHWSJnbm2X0WNg= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Harigovindan P , Jeffrey Hugo , Rob Clark , Sasha Levin Subject: [PATCH 5.4 028/168] drm/msm/dsi/pll: call vco set rate explicitly Date: Tue, 10 Mar 2020 13:37:54 +0100 Message-Id: <20200310123638.458706602@linuxfoundation.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200310123635.322799692@linuxfoundation.org> References: <20200310123635.322799692@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Harigovindan P [ Upstream commit c6659785dfb3f8d75f1fe637e4222ff8178f5280 ] For a given byte clock, if VCO recalc value is exactly same as vco set rate value, vco_set_rate does not get called assuming VCO is already set to required value. But Due to GDSC toggle, VCO values are erased in the HW. To make sure VCO is programmed correctly, we forcefully call set_rate from vco_prepare. Signed-off-by: Harigovindan P Reviewed-by: Jeffrey Hugo Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 8f6100db90ed4..aa9385d5bfff9 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -411,6 +411,12 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw) if (pll_10nm->slave) dsi_pll_enable_pll_bias(pll_10nm->slave); + rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0); + if (rc) { + pr_err("vco_set_rate failed, rc=%d\n", rc); + return rc; + } + /* Start PLL */ pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x01);