From patchwork Fri Feb 21 07:38:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 230945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F4EAC35641 for ; Fri, 21 Feb 2020 08:07:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1D55E20578 for ; Fri, 21 Feb 2020 08:07:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582272439; bh=Axi621C+trmYJ2hkH6lGnJy9hkrtz3txnGYSyx8Bdg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=t96wkXBxckj1dJdPAArTsYbj6S8JFYTdetWilXXXVwJiVSdC95qGRP1MoHkH8hWVx HJ0iQOu4c/MvfdxR/6eLlrD0D7FU2jtsqDEUBWcSxknP3K2QEaE9oiNAgh+NdiuQbV zx80jKdtD1+kIq3LCS2NKzVYpwTDwlNkJ2r6pUaI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731921AbgBUIHS (ORCPT ); Fri, 21 Feb 2020 03:07:18 -0500 Received: from mail.kernel.org ([198.145.29.99]:41434 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731133AbgBUIHR (ORCPT ); Fri, 21 Feb 2020 03:07:17 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 72E4320722; Fri, 21 Feb 2020 08:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1582272436; bh=Axi621C+trmYJ2hkH6lGnJy9hkrtz3txnGYSyx8Bdg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LHMfnWHNOojvlgWqrZT3lZIcaEphpPM2N2YSTQRYrFkMXWCcY5lGiMdGp0qQKbnCF mRq/V5TULPiS58cy4emqP67q6X+THiWtBexQwgPgqghZLL+CDvmBjn8KjtV52htU8m bNGk4GuR6RQuj1bA8xuCSk2Al5vzxe/xEJumQaoA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Andre Przywara , Maxime Ripard , Sasha Levin Subject: [PATCH 5.4 108/344] arm: dts: allwinner: H3: Add PMU node Date: Fri, 21 Feb 2020 08:38:27 +0100 Message-Id: <20200221072358.732867183@linuxfoundation.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200221072349.335551332@linuxfoundation.org> References: <20200221072349.335551332@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Andre Przywara [ Upstream commit 0388a110747bec0c9d9de995842bb2a03a26aae1 ] Add the Performance Monitoring Unit (PMU) device tree node to the H3 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on an OrangePi Zero. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin --- arch/arm/boot/dts/sun8i-h3.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index e37c30e811d3b..6056f206c9e39 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -80,7 +80,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; @@ -90,7 +90,7 @@ #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; @@ -100,7 +100,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -111,6 +111,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = ,