From patchwork Mon Feb 10 12:32:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 232013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC39C352A3 for ; Mon, 10 Feb 2020 12:38:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B291D2173E for ; Mon, 10 Feb 2020 12:38:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581338300; bh=u4syaK1k26muVpgB7yUZuhhiC8BPnRluHbUUcVDMsoU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=SGhxWH72d49eDGUDquRnMBuiV685UG0/EpZFtLbf1jgSC//ITFWl33FyXLvPOuvPc 19AfIijbE8ZJ4kszav6LIgncIxWOEfDuBGtSnkhoPxVK9P8EA/XgityeGSO5ChGpUj 0uHgEchpkk+h9Lr6VVvDJqkHGr/WARLUkDssA8mY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729113AbgBJMiT (ORCPT ); Mon, 10 Feb 2020 07:38:19 -0500 Received: from mail.kernel.org ([198.145.29.99]:33588 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729110AbgBJMiT (ORCPT ); Mon, 10 Feb 2020 07:38:19 -0500 Received: from localhost (unknown [209.37.97.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 9DE8B2465D; Mon, 10 Feb 2020 12:38:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581338298; bh=u4syaK1k26muVpgB7yUZuhhiC8BPnRluHbUUcVDMsoU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O4stu4tjf4P9rX0O3gle01F4nJzQFUXA/knBCF+Hqc49idg62naUNpijIFqchxHBT H4dp3DoK62/BIY6Yqt8pAsVlPIxTwAoN2h0je6FhZsdhi43vxqN6lgYjhS3XUNXTZs UNE2RFa3iktbST8SckEcr3iqQmCr8+aSYFNCJvDQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Nick Finco , Marios Pomonis , Andrew Honig , Jim Mattson , Paolo Bonzini Subject: [PATCH 5.4 207/309] KVM: x86: Protect MSR-based index computations from Spectre-v1/L1TF attacks in x86.c Date: Mon, 10 Feb 2020 04:32:43 -0800 Message-Id: <20200210122426.439512225@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200210122406.106356946@linuxfoundation.org> References: <20200210122406.106356946@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marios Pomonis commit 6ec4c5eee1750d5d17951c4e1960d953376a0dda upstream. This fixes a Spectre-v1/L1TF vulnerability in set_msr_mce() and get_msr_mce(). Both functions contain index computations based on the (attacker-controlled) MSR number. Fixes: 890ca9aefa78 ("KVM: Add MCE support") Signed-off-by: Nick Finco Signed-off-by: Marios Pomonis Reviewed-by: Andrew Honig Cc: stable@vger.kernel.org Reviewed-by: Jim Mattson Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/x86.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2494,7 +2494,10 @@ static int set_msr_mce(struct kvm_vcpu * default: if (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(bank_num)) { - u32 offset = msr - MSR_IA32_MC0_CTL; + u32 offset = array_index_nospec( + msr - MSR_IA32_MC0_CTL, + MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); + /* only 0 or all 1s can be written to IA32_MCi_CTL * some Linux kernels though clear bit 10 in bank 4 to * workaround a BIOS/GART TBL issue on AMD K8s, ignore @@ -2921,7 +2924,10 @@ static int get_msr_mce(struct kvm_vcpu * default: if (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(bank_num)) { - u32 offset = msr - MSR_IA32_MC0_CTL; + u32 offset = array_index_nospec( + msr - MSR_IA32_MC0_CTL, + MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL); + data = vcpu->arch.mce_banks[offset]; break; }