| Message ID | 20191024124833.4158-28-ard.biesheuvel@linaro.org |
|---|---|
| State | New |
| Headers | show
Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2142667ill; Thu, 24 Oct 2019 05:49:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqw1w55pC5X/rNG5PivtHYAZE1siMiubFD1ekw9lGHBK3Qr9ms61tdUHLcOgL7E5l9qt4AnP X-Received: by 2002:a17:906:35cb:: with SMTP id p11mr38401444ejb.128.1571921377225; Thu, 24 Oct 2019 05:49:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571921377; cv=none; d=google.com; s=arc-20160816; b=DN1KlXeQvE8arBcZ86nn55sVlBTQTvly4sE1C70BTzGyHikjIP8OaKhEMRASXsczBN A0qYlin1lGe4BugoT+qf3r0k/VBa4plQxr4wTBr7msnEkD/v82gYtQzP86zCt0Of/u/I ayuxVV7JE2UnwfMSqahjBKy8tmOfU4Miau2rP87RwKJ0lnM1vxF4vH8xkM1RDjjSI5J+ lKNZuejeLrIRJ5i0X1JGin7KFmKL+Vf5S8p1OCafFLfK0juVrHeJJrGwysMx0g+lP4Wh en4t5VMZsAsLEtC3BSFO3ZEaT7kN+jTth2eF9zaUSAJaA4kBYg20owViouCYs7J/9Rau xvLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iH5ScDlNm2VFRLMaaO2Sqe3ThsWOiflSACcQzmSoM8w=; b=GQo5CeW1Qm/0AHdnBwx+mL0U+0X8XMklQoEgW+kyrkR04JPk4SMYzBphINXnv1syTr crUXO0xj0xGKJFohg748RZP3yd8Y2FD0w4mR7VqPNNpkJVpt1SJJr2jix8mioXCywli3 CM2IB7tOmIW5BIZDLmL0YohLvnMStP30fyOXiVLCAXQlcmY3wrQJY6S1NlPdc1aSyk8B lRJCHNm80nReL4c+5u6X8kVpnI6oCTrVa5TAUmSsUPXY+6ncliVT+lB62T09CgE2pdxn L7DZHhqI2k3Lk3sBhdbmCqJXF3FayqSMPecCXTfNVd3Gryf493XX1MGNvsyn7murSQSi trcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eZoJfXp+; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: <stable-owner@vger.kernel.org> Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f3si12973378eda.251.2019.10.24.05.49.37; Thu, 24 Oct 2019 05:49:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eZoJfXp+; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502106AbfJXMtg (ORCPT <rfc822;lee.jones@linaro.org> + 14 others); Thu, 24 Oct 2019 08:49:36 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40576 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2502111AbfJXMtg (ORCPT <rfc822;stable@vger.kernel.org>); Thu, 24 Oct 2019 08:49:36 -0400 Received: by mail-wm1-f65.google.com with SMTP id w9so1306314wmm.5 for <stable@vger.kernel.org>; Thu, 24 Oct 2019 05:49:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iH5ScDlNm2VFRLMaaO2Sqe3ThsWOiflSACcQzmSoM8w=; b=eZoJfXp+/10GbeXcIEIPwWN9yVSLaInOBHTMOyrydvHnh4CPncPQ3qS7uSZw99Lb88 D9/2ufoJRjmlFe6iJR0Lc7AoFeq5Dwgx+/OTpczefbbwbVIFsB+1lAVNgCurkteQALoy oLwtW+XECd91hkUrEwTfbt9FZOprTUkAACHciDtPvEG/SKyTff6SLn2lQT6VD83kKkbn 5fRVWYE3IMgHSJw+/bL8iMjkbwE9toGvsTCPvO4LiS2LPJoPpxkCLxwLtls5sGyTRyKv JAqIqKdNpPetBRvFohdsKvSEk9O2z2sUszSLDtDLBO2YCzr8bN3iAwxhuNmsLTiV5K7E nDFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iH5ScDlNm2VFRLMaaO2Sqe3ThsWOiflSACcQzmSoM8w=; b=l/0xzVW284b5bCr18W03F1XfPM9pH1sHB1/TDjdKPpI+AliYnFAzutasCHBa4IRyzU 9lN+hr3BSueiPiId2VzIiLpOyjPGIjU651hOLoaY6DgyABPYgUZANQycphB5nl+6R/tH kuZKZrF+NvUjot1t+eGdyHQwyi0eanpYjuoCUj/yXAcR0rekXMX34oWs8B5O0WapYxh8 g8YH9at7HsKJbJnqNSpTodFtY399HXRrqBraTwL7LEZm2XjrkF73hMKd1tPl9fsVaGVM MBHA7yuiRm2WKj+rWZmVwoJybHIhznV2awkNFKrNdMO7q84pb8RQqicL6IsVqwRWUnU8 hNpg== X-Gm-Message-State: APjAAAWt4fvMKbIa/tQswpIHXJUw4BojlwHAtzZfMy3fOOW9mdhHtq5D Iomw/UXapRQl9LMMJutFW3q5NXUSN0/80FC2 X-Received: by 2002:a7b:cbc6:: with SMTP id n6mr2627016wmi.161.1571921372479; Thu, 24 Oct 2019 05:49:32 -0700 (PDT) Received: from localhost.localdomain (aaubervilliers-681-1-126-126.w90-88.abo.wanadoo.fr. [90.88.7.126]) by smtp.gmail.com with ESMTPSA id j22sm29111038wrd.41.2019.10.24.05.49.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 05:49:31 -0700 (PDT) From: Ard Biesheuvel <ard.biesheuvel@linaro.org> To: stable@vger.kernel.org Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Jeremy Linton <jeremy.linton@arm.com>, Andre Przywara <andre.przywara@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Dave Martin <dave.martin@arm.com>, Will Deacon <will.deacon@arm.com> Subject: [PATCH for-stable-4.14 27/48] arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35 Date: Thu, 24 Oct 2019 14:48:12 +0200 Message-Id: <20191024124833.4158-28-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191024124833.4158-1-ard.biesheuvel@linaro.org> References: <20191024124833.4158-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: <stable.vger.kernel.org> X-Mailing-List: stable@vger.kernel.org |
| Series |
arm64 spec mitigation backports
|
expand
|
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index c60eb29ea261..ef03243beaae 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -85,6 +85,8 @@ #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A73 0xD09 #define ARM_CPU_PART_CORTEX_A75 0xD0A +#define ARM_CPU_PART_CORTEX_A35 0xD04 +#define ARM_CPU_PART_CORTEX_A55 0xD05 #define APM_CPU_PART_POTENZA 0x000 @@ -108,6 +110,8 @@ #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) +#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)