From patchwork Wed May 22 13:22:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 164825 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp860557ili; Wed, 22 May 2019 06:24:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqwUvSpyUsFkfIASmIjyRHAeemBNPaGTbfKGtOavEiLmIpVUIWayRawwYWWz7Yj4IoDJK+/C X-Received: by 2002:a65:56c5:: with SMTP id w5mr90306685pgs.434.1558531484229; Wed, 22 May 2019 06:24:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558531484; cv=none; d=google.com; s=arc-20160816; b=zUcfKYBNIxExB5fRqxEGLAUe6hWF18Lf0Cv0pPMfMfoSTHI8jlTz6MCLyJC5c2YHWr WsdGVdHI5Kdj+KQWFgPblEOYA5cQvcSK+7xZoetCaJ1aL7eToDAs421nzmm7qhXC9S63 /NxE4p8/e/0V/3Dz5V0JLwTM7Xc/2/i/+ZwZ+h+zjUdnw9bJfeUPXU5fm6nu2Bkp85C9 llQhRonZVsJIPpSHRmLgkeAlhnmYMiUItIbRplkfvdVDRLnSuRrOgVK0Hz31xPh/2lOB pVVjtc8Ge/QH8Zr9qWJpwNdF7aWC4ihXxHSsmta4OwaReWis5IDep5KdrXpPF91bsdxu CYBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=8jGhecHXi8esBoyZgI3ujmIDhtN4iwcR41K3iJO1Tw4=; b=t1vLo9JVc3v9ka57R26cCKttIAOi4+oBnztsOKPpSfQR5n5ewJcXn6+tgvrzpjwgXu 7tqKmrYfB4WFW+gxlsArva+hBnTYQnPJ0CIipA5HvsZxkGaflWp2ivYOjFBJCN4kFRmu G2VLNvqCthszovRFjW3GQWyaoZGnOGiSSdq4YoGHw4bimJ7K3XD+mAgs1IGEvg4dfbzf vUecE/UvxFUHEGUR4q4aJv6Qt60OYy5U6N/0MRfYB/WVyxXmYSBL+Fwbf6uM0mFCA/t0 5JA18JQHMP3+FYZpIcYziNhzVEGcWQfKtQycuFBHBbxTnriqpBwhfn9jhzZk0McZMpvQ 1ihg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h5si27216435pgg.526.2019.05.22.06.24.44; Wed, 22 May 2019 06:24:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729609AbfEVNYn (ORCPT + 14 others); Wed, 22 May 2019 09:24:43 -0400 Received: from foss.arm.com ([217.140.101.70]:50872 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729059AbfEVNYn (ORCPT ); Wed, 22 May 2019 09:24:43 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDE5880D; Wed, 22 May 2019 06:24:42 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7C2A83F575; Wed, 22 May 2019 06:24:38 -0700 (PDT) From: Mark Rutland To: linux-kernel@vger.kernel.org, peterz@infradead.org, will.deacon@arm.com Cc: aou@eecs.berkeley.edu, arnd@arndb.de, bp@alien8.de, catalin.marinas@arm.com, davem@davemloft.net, fenghua.yu@intel.com, heiko.carstens@de.ibm.com, herbert@gondor.apana.org.au, ink@jurassic.park.msu.ru, jhogan@kernel.org, linux@armlinux.org.uk, mark.rutland@arm.com, mattst88@gmail.com, mingo@kernel.org, mpe@ellerman.id.au, palmer@sifive.com, paul.burton@mips.com, paulus@samba.org, ralf@linux-mips.org, rth@twiddle.net, stable@vger.kernel.org, tglx@linutronix.de, tony.luck@intel.com, vgupta@synopsys.com Subject: [PATCH 08/18] locking/atomic: ia64: use s64 for atomic64 Date: Wed, 22 May 2019 14:22:40 +0100 Message-Id: <20190522132250.26499-9-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190522132250.26499-1-mark.rutland@arm.com> References: <20190522132250.26499-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org As a step towards making the atomic64 API use consistent types treewide, let's have the ia64 atomic64 implementation use s64 as the underlying type for atomic64_t, rather than long or __s64, matching the generated headers. As atomic64_read() depends on the generic defintion of atomic64_t, this still returns long. This will be converted in a subsequent patch. Otherwise, there should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Fenghua Yu Cc: Peter Zijlstra Cc: Tony Luck Cc: Will Deacon --- arch/ia64/include/asm/atomic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.11.0 diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h index 206530d0751b..50440f3ddc43 100644 --- a/arch/ia64/include/asm/atomic.h +++ b/arch/ia64/include/asm/atomic.h @@ -124,10 +124,10 @@ ATOMIC_FETCH_OP(xor, ^) #undef ATOMIC_OP #define ATOMIC64_OP(op, c_op) \ -static __inline__ long \ -ia64_atomic64_##op (__s64 i, atomic64_t *v) \ +static __inline__ s64 \ +ia64_atomic64_##op (s64 i, atomic64_t *v) \ { \ - __s64 old, new; \ + s64 old, new; \ CMPXCHG_BUGCHECK_DECL \ \ do { \ @@ -139,10 +139,10 @@ ia64_atomic64_##op (__s64 i, atomic64_t *v) \ } #define ATOMIC64_FETCH_OP(op, c_op) \ -static __inline__ long \ -ia64_atomic64_fetch_##op (__s64 i, atomic64_t *v) \ +static __inline__ s64 \ +ia64_atomic64_fetch_##op (s64 i, atomic64_t *v) \ { \ - __s64 old, new; \ + s64 old, new; \ CMPXCHG_BUGCHECK_DECL \ \ do { \ @@ -162,7 +162,7 @@ ATOMIC64_OPS(sub, -) #define atomic64_add_return(i,v) \ ({ \ - long __ia64_aar_i = (i); \ + s64 __ia64_aar_i = (i); \ __ia64_atomic_const(i) \ ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \ : ia64_atomic64_add(__ia64_aar_i, v); \ @@ -170,7 +170,7 @@ ATOMIC64_OPS(sub, -) #define atomic64_sub_return(i,v) \ ({ \ - long __ia64_asr_i = (i); \ + s64 __ia64_asr_i = (i); \ __ia64_atomic_const(i) \ ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \ : ia64_atomic64_sub(__ia64_asr_i, v); \ @@ -178,7 +178,7 @@ ATOMIC64_OPS(sub, -) #define atomic64_fetch_add(i,v) \ ({ \ - long __ia64_aar_i = (i); \ + s64 __ia64_aar_i = (i); \ __ia64_atomic_const(i) \ ? ia64_fetchadd(__ia64_aar_i, &(v)->counter, acq) \ : ia64_atomic64_fetch_add(__ia64_aar_i, v); \ @@ -186,7 +186,7 @@ ATOMIC64_OPS(sub, -) #define atomic64_fetch_sub(i,v) \ ({ \ - long __ia64_asr_i = (i); \ + s64 __ia64_asr_i = (i); \ __ia64_atomic_const(i) \ ? ia64_fetchadd(-__ia64_asr_i, &(v)->counter, acq) \ : ia64_atomic64_fetch_sub(__ia64_asr_i, v); \