From patchwork Wed Oct 31 14:04:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149826 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836100ljp; Wed, 31 Oct 2018 07:04:50 -0700 (PDT) X-Received: by 2002:a67:87cf:: with SMTP id j198mr632866vsd.104.1540994690316; Wed, 31 Oct 2018 07:04:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994690; cv=none; d=google.com; s=arc-20160816; b=b41oflOTl6bbdBz36SgXTSqXsRt0hFiKICXniyIPyMCQfkzP9luEyNpxa4E8dZSH4P ClDBahKrlQz//Ios8bzfc/dbFD+acflY0KLWbJIOt1QbV5UKJ3jrXphwWJJScX/FNxd5 m+bsCLCPChDUHwqSrtR7HfQ8XnqcYLZghAuZMjykUQ7FVJYATLEe2H92jZuyy/AIP95H CnhthCcRgLOneLcVCMG0sXevBB/5WkAHj6WRq4moP/6m5WjhyqsQ51JLOM4VMPQKA5bn sXnZow/3mnEReQkXk6ZVivu21wB12Ef5806v6Dp443pU15N13fgwDw0aScf10bctR5TS Srbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=LByArq2p1H87yf6nZmMVru66da2ZkCDT89sJjrStFkeGdoDz6l727Gr+pFIypg04A4 OL/wgsK/gLuQmS5Q/2Erzh2WPcCCCDWNuV9EoHsgPhSJCPChOjgGILmzzy02uYHORvj/ Ezv7fCisrpPdAO6fdyAY11fsbu5UgY+SJMxxJC0ozwcx8rynKwZtIYd2mxw/B9rFT0bW uQ4MSWyZoF750ayZsPJaZ29jHCfALB2TptpqhJ5Zu8xbE9OTGfaKH5+xTO2Egs7tqvhk i2GVq5FiKNCqJOXauwt2hEdgqDNWNvpLRtSAm6KWtufi04A5Axd+wh02tUvGfv3vpP1Y DRFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bThnRVgQ; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w18sor16273332uaj.58.2018.10.31.07.04.50 for (Google Transport Security); Wed, 31 Oct 2018 07:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bThnRVgQ; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=bThnRVgQET4Lz6iWI+LjvuQho1FoWcdO/PWwJOCYNYxp2DXcxauevFjbD4Da8cQB1y 82m8w8uhRwbtG5FalmeRpTC0KvT97fHNofEE19cu5yjrL5Q8B/KffLpiwzyjRe6C+tR6 2d+cpsL/MGrM6dVasH7rk86LFfGUV3P6WWUkc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HEne2njS0TPSGIgg0dgG4R5OFKIAKRCc8fMLUGG3Bbk=; b=l3+78ZyPnCDxakP15nh7L7uRlFLcN76LvHvL9wShZpexM8boqVHBRc8S4JOIPFaj0n rrGPri4z+RUx6huX1+Oix640pODO50/KNICaG/SI7wXgvjUk+825MVThaxAgsUJihj7o 0Ds4DZivgpD+/LEYtP7e2BZ3svtcPB4D7sO9qBQtNr3p7zQEe+J3rlLIzxhtR5ZQ3VtV Kw8sgfNc84bdt+yR1TkoS6mTySqgjTMPywiTsSSEB2nO+AilPMx1GM1JlGXgREfY7t3M cay+zN6Lr7QueMLvN7NnIq/m4btfucruy6bbhh9fxY+QpB7rFgxIlr9IOe47P4LMcmPE Zn6g== X-Gm-Message-State: AGRZ1gJysIUJD4kJII28pRkQxAFuAQ4OO3U84WggPGBy9xUAC1mI0ZM9 6UaoxksNoUmVcNvBD0RNWJlxxoS+ X-Google-Smtp-Source: AJdET5etLHVe+uwkU+SLxGCT+pqendR62nkPcQOe5J5qGxeM+/D2/XOJ9+v+fUXCtqoVDEj4mnoOxQ== X-Received: by 2002:ab0:b82:: with SMTP id c2mr1428137uak.121.1540994689690; Wed, 31 Oct 2018 07:04:49 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:48 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 07/18] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit Date: Wed, 31 Oct 2018 10:04:25 -0400 Message-Id: <20181031140436.2964-8-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit e388b80288aade31135aca23d32eee93dd106795 upstream. When the branch predictor hardening is enabled, firmware must have set the IBE bit in the auxiliary control register. If this bit has not been set, the Spectre workarounds will not be functional. Add validation that this bit is set, and print a warning at alert level if this is not the case. Signed-off-by: Russell King Reviewed-by: Florian Fainelli Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/mm/Makefile | 2 +- arch/arm/mm/proc-v7-bugs.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mm/proc-v7.S | 4 ++-- 3 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mm/proc-v7-bugs.c -- 2.17.1 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 7f76d96ce546..35307176e46c 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -92,7 +92,7 @@ obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V6K) += proc-v6.o -obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o obj-$(CONFIG_CPU_V7M) += proc-v7m.o AFLAGS_proc-v6.o :=-Wa,-march=armv6 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c new file mode 100644 index 000000000000..e46557db6446 --- /dev/null +++ b/arch/arm/mm/proc-v7-bugs.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +static __maybe_unused void cpu_v7_check_auxcr_set(bool *warned, + u32 mask, const char *msg) +{ + u32 aux_cr; + + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr)); + + if ((aux_cr & mask) != mask) { + if (!*warned) + pr_err("CPU%u: %s", smp_processor_id(), msg); + *warned = true; + } +} + +static DEFINE_PER_CPU(bool, spectre_warned); + +static void check_spectre_auxcr(bool *warned, u32 bit) +{ + if (IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && + cpu_v7_check_auxcr_set(warned, bit, + "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); +} + +void cpu_v7_ca8_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)); +} + +void cpu_v7_ca15_ibe(void) +{ + check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)); +} diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index c2950317c7c2..1436ad424f2a 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -511,7 +511,7 @@ __v7_setup_stack: globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca8_do_resume, cpu_v7_do_resume #endif - define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe @ Cortex-A9 - needs more registers preserved across suspend/resume @ and bpiall switch_mm for hardening @@ -544,7 +544,7 @@ __v7_setup_stack: globl_equ cpu_ca15_suspend_size, cpu_v7_suspend_size globl_equ cpu_ca15_do_suspend, cpu_v7_do_suspend globl_equ cpu_ca15_do_resume, cpu_v7_do_resume - define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 + define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe #ifdef CONFIG_CPU_PJ4B define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 #endif