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[209.85.220.65]) by mx.google.com with SMTPS id t4sor16126487vsa.43.2018.10.31.07.04.56 for (Google Transport Security); Wed, 31 Oct 2018 07:04:56 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=STUl5Yof; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w3vN2kbKb/kbQFzTan22brttmozPByYhPX1tSkHW2yg=; b=STUl5YofniCjcwN5T161W4MyVgqI+BR29z63vStJnovJLgPmpJL2pB+F47OIaWJep4 m/qKqPjB2kHjPJPosSpLKGc9GglwksIke68X9mIEAvaw+8mYS719+GqcOgddit+uQw8x gk63Y9qWBYQHqKxlWl4vKaEwozjEAi4+aDx0Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w3vN2kbKb/kbQFzTan22brttmozPByYhPX1tSkHW2yg=; b=p57NoTT40sDAIkNbtDTBGlpkQLnZQCEzo69kPuEKUC5DXn03VADUvcwcLNvdzGjOs+ mhInp5mrSw+11ZitAUZ2ltMH2xxUyFM4yQO9DaiZn3BvH5NcsTXnpKJ+x28xkdG5vBns rPnNJ4K5Bkl8rddmXVnzCn+xqoXWJOOcIqVFS67BBu0F3ZWkt6vXxyb5aeWMdHwR7bWt 1Z8PHbVdDb8dc8CQBnvNf4AwixZa83sDoBSOrH54h60sSn3cjRqrvIaap3DuFc/yPxkx pvlC+rLfKMaSIye5vuWaoD9a8wcIzwcBXM7prX6mEPwFrHs2PmHPPezdvGT+yI6zGDUT kkPA== X-Gm-Message-State: AGRZ1gKO+8s7ADPG7f3vrUZTwdCxaxpqMzofY+X/RRl2KBpmziQz5e67 5tdsN4mBXsFNf0KjVgk/xVQMoxdg X-Google-Smtp-Source: AJdET5f0g1dmpoF9Dkr/VU5nLPVQt/U4r2tC+J6LA8A0zvzIGgrJOkQNk1CSDDqhn9MXuRGc3XkpaQ== X-Received: by 2002:a67:bc1:: with SMTP id 184mr1309593vsl.153.1540994695876; Wed, 31 Oct 2018 07:04:55 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:55 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 11/18] ARM: spectre-v1: add array_index_mask_nospec() implementation Date: Wed, 31 Oct 2018 10:04:29 -0400 Message-Id: <20181031140436.2964-12-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit 1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613 upstream. Add an implementation of the array_index_mask_nospec() function for mitigating Spectre variant 1 throughout the kernel. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/barrier.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index d705be47a1ad..85eb7ef44a18 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -106,5 +106,24 @@ do { \ #define smp_mb__before_atomic() smp_mb() #define smp_mb__after_atomic() smp_mb() +#ifdef CONFIG_CPU_SPECTRE +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + "cmp %1, %2\n" + " sbc %0, %1, %1\n" + CSDB + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + return mask; +} +#define array_index_mask_nospec array_index_mask_nospec +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_BARRIER_H */