From patchwork Wed Oct 31 14:04:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149829 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6836215ljp; Wed, 31 Oct 2018 07:04:55 -0700 (PDT) X-Received: by 2002:a67:843:: with SMTP id 64mr1348502vsi.166.1540994694984; Wed, 31 Oct 2018 07:04:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994694; cv=none; d=google.com; s=arc-20160816; b=sVIN0Y7+nTVqvXAYPHlK2h+N8ewT5dncHVo/+osFvGDiDBLciheSXYkaAKygBzY0z6 Kwcx60CnY9WE80a319oxWtCNhtyGXKc3RYnLC0uCSvSaLxc7J8OIBW/WLrp5fDBBao02 mqWnhwj/PchrtAWHPmeKS2qCydshT+MDhuk3rgZgBnp6LcKOxyS8txOkGFDxlZ8PTrSC hEtCNRTj593gp0hu20BPH6HUfKpyv/A46S+b5/ZV3jZtBSZ7tTKHyJGHY0sgmyo5U6hz s6mU+OqjcurPMn3idbUZZHvSyFVJ/Es0oTbUMyckhZ6cUK0CtV7S3fOQW+a38u6SBS2v PNlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=I+IEr7JzE0FLXVRFj3iNGuUrmbre2Fhx4ta8oqZzp61p3oofBYAEoq6c2d11IGJ46J U/JXl6RxYre2ZYcmYC8j51Skz9Z8WxS/iDlyVeVV1HxhZQlu/k+yz3L0PPVH2gG7KVBi eR29JZ7LIrtaMMjgTslnIj2rV+kFCmwSKTNYUhBIznhxp87W3165wqbGbylpnIMlnrxO CRYfr93QyhaP34jZCZObDeL/tMKPy6YIdguLr8+nkbMXYwbjM9gdje0lFgJVX+bHFrU/ uFcCByY/IFfSHN5Zb2uXRlp+1m10rG0uD5bOS2gXCfQvLyhu8VJR/QY13KeJpnnDyhis aBTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6v5uzAF; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id r134sor1213171vsc.112.2018.10.31.07.04.54 for (Google Transport Security); Wed, 31 Oct 2018 07:04:54 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g6v5uzAF; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=g6v5uzAF3qUXVjklFMYFzqczf18m7XMmercqnWO/K3DNCTccdZ0Vq7juTTbWkkJEf3 +es1Zp4TxdRKQxvZOCeKbMwzvBVXuyES4ByCkYkA5qZKtW7E2S891WPVw/UTxG79pT/E OlAipQ0Np8easI7ivf5pWRT8MILp8yDyV6Abc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u2E0Yv/m/5J4oG7CM84UYhk7NYJmPFxPsB+ynyFPbSs=; b=OJmFLiMxm66blge733rgdJ2Qq6wGg4mii9zVh1D+fJA9jNn8K/6wvHnat7wAk/Y4+F NW3TUU/nUvZQZjdtQ1JvN0lD/0V+vWN03zTgdbUHhxo2rMANwtOqVfRuBlEGlDo6ewdg T+fVD2OU205y7lAIatmxeswNeCjaFdhyXa9P4kRdVEZaKWhboaeu3V2hvGnJ2Cckw2s+ 5NilTBso4zETC5LlxEwFshYohsFXZRmtVQ+rwWa2QCSojEh/PdQIOsU1+ozdmsVivL4l 5Q1ftSe3HlZX/u5U4c7WWay5ovVLD4Bq/PaXkbTmZpZaOup9Tfc6altaBXfMFDlaNi1S kLDA== X-Gm-Message-State: AGRZ1gK5eI3xQjuYQDF1ZnXsYshXFIluHf2xp1Bl+o6WCByIs/bXqR6m 0s+UDiKHrvZyqZCOn6r8p6HXN1HN X-Google-Smtp-Source: AJdET5enYe5EgvpyJHiIHraDNt6eodlHikioMWR8GLZdT9/37J7lwXfK5nfuaCGknmjtGTmDAe9JIA== X-Received: by 2002:a67:98c3:: with SMTP id g64mr1356311vsh.204.1540994694361; Wed, 31 Oct 2018 07:04:54 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:53 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 10/18] ARM: spectre-v1: add speculation barrier (csdb) macros Date: Wed, 31 Oct 2018 10:04:28 -0400 Message-Id: <20181031140436.2964-11-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit a78d156587931a2c3b354534aa772febf6c9e855 upstream. Add assembly and C macros for the new CSDB instruction. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/barrier.h | 13 +++++++++++++ 2 files changed, 21 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 4a275fba6059..307901f88a1e 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -441,6 +441,14 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .size \name , . - \name .endm + .macro csdb +#ifdef CONFIG_THUMB2_KERNEL + .inst.w 0xf3af8014 +#else + .inst 0xe320f014 +#endif + .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req #ifndef CONFIG_CPU_USE_DOMAINS adds \tmp, \addr, #\size - 1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 3ff5642d9788..d705be47a1ad 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -16,6 +16,12 @@ #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") +#ifdef CONFIG_THUMB2_KERNEL +#define CSDB ".inst.w 0xf3af8014" +#else +#define CSDB ".inst 0xe320f014" +#endif +#define csdb() __asm__ __volatile__(CSDB : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -36,6 +42,13 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifndef CSDB +#define CSDB +#endif +#ifndef csdb +#define csdb() +#endif + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void);