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[209.85.220.65]) by mx.google.com with SMTPS id d81-v6sor13358468vkd.2.2018.10.31.07.04.53 for (Google Transport Security); Wed, 31 Oct 2018 07:04:53 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hfqzVOtP; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a96yTV8wn2l6+VBtY/7yxFV7aynWWpJdrxYm6O/2iOk=; b=hfqzVOtPZO9Kf2pDXqek2I53fQsJ0KTPVZ6G8kS1cVlVnw5dEqVUYkazQuFD0sVF60 KoRwjHphZbc8vXAeWcopucS3moDWU3OXduDkXOl5b2XGURq81cntYMzMa4IuqRq4dJOp JqWGn3SOfWwh7FIIy50VCQX25SN93ywlvL1yk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a96yTV8wn2l6+VBtY/7yxFV7aynWWpJdrxYm6O/2iOk=; b=TOMN7Gug/dn08x7NLJIBmQQmswvDbn9FIAOzCq4UINRKDf0lV/pewWDwoiKxhJ3IDz /s81bb9a4dLYiC+2iz6fvCSlaKCy3RKniSgiwmdZMI+o8CeBWQBTF86qJ/wnCMNR8Daa 5CfMU3kqF+UZ/0HAew1Rj7dOqgI8OwgmKFqENJjMStWpuZfdn5TBbPFW7kYmnmi0F2/2 oBt1OMv9vNQslP6K8/6dc5PnQxor27Jdf3ZXgZ0Two3gIYcQlgH3zZoRnxAQjBZHaw+h Bir/IAhD8CSVoQHEm9ldk78g71fcSiEiAv6BSvi0G/OsSUuTV4c7nYXd1kQN5S1wCRba AMtg== X-Gm-Message-State: AGRZ1gIei1qqqM4y2LO8U5vprjGYg+3ydoe0XKpUF3TSv01Pvqj6Lvrv ao7G3gmN8qHxxAsbt98FKDthCJTC X-Google-Smtp-Source: AJdET5dStCsNbWPWxiqsmv4nlWR+GG/ZT8u20H62/A+Nd9Ep7hL8mQjrUD822zT7bso6/MgcZsmY8g== X-Received: by 2002:a1f:1e09:: with SMTP id e9mr1390408vke.18.1540994692862; Wed, 31 Oct 2018 07:04:52 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id 6sm6795632vsy.25.2018.10.31.07.04.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 07:04:52 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.4 09/18] ARM: spectre-v2: warn about incorrect context switching functions Date: Wed, 31 Oct 2018 10:04:27 -0400 Message-Id: <20181031140436.2964-10-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031140436.2964-1-dave.long@linaro.org> References: <20181031140436.2964-1-dave.long@linaro.org> From: Russell King Commit c44f366ea7c85e1be27d08f2f0880f4120698125 upstream. Warn at error level if the context switching function is not what we are expecting. This can happen with big.Little systems, which we currently do not support. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/mm/proc-v7-bugs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index 85a2e3d6263c..027b29f852f6 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -4,11 +4,15 @@ #include #include +#include #include #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); +extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); + static void harden_branch_predictor_bpiall(void) { write_sysreg(0, BPIALL); @@ -34,6 +38,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A17: case ARM_CPU_PART_CORTEX_A73: case ARM_CPU_PART_CORTEX_A75: + if (processor.switch_mm != cpu_v7_bpiall_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_bpiall; spectre_v2_method = "BPIALL"; @@ -41,6 +47,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A15: case ARM_CPU_PART_BRAHMA_B15: + if (processor.switch_mm != cpu_v7_iciallu_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; @@ -49,6 +57,11 @@ static void cpu_v7_spectre_init(void) if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); + return; + +bl_error: + pr_err("CPU%u: Spectre v2: incorrect context switching function, system vulnerable\n", + cpu); } #else static void cpu_v7_spectre_init(void)