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[209.85.220.65]) by mx.google.com with SMTPS id 3sor5427797vsr.31.2018.10.31.06.57.37 for (Google Transport Security); Wed, 31 Oct 2018 06:57:37 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T89PTQsK; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CEkLCWkfi7hEmbdyVA5A/qugIy7C6sSql4wlvQw1hos=; b=T89PTQsKIfLjzVzxaYHancAz13rLcTSdhmwGcfLYXafJmojeLCTgiAg9KAhbQifZaC 10dG00UAXZkpg0JMAQ78YWgxekGPaD6VUL8wiETJSYYbe9/aQkqxlDQZ/jjZcqWvBLcR s7OoWyKHYoG4ie7yyhtvZCgQOl2py5Rjf3QVI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CEkLCWkfi7hEmbdyVA5A/qugIy7C6sSql4wlvQw1hos=; b=ByTvfPcRqQgLD46hW0dCcfy1hGzsqw4s9Ffm1hJFwR7D8H5aAKsrPXpYRs8VxCAwUh iGV9iL+04cGqvReuuNAi1wx+ZOSO0qPD2vJphryV3pLzMrNs2yPQ9qA0MgX4597Cgary bWnlrtAs/QtJeiielF/O6Qththz3feoXyg7IqUhlx6mRmbezAY87VZ3b3H+oqo0e1gv7 rrJDiuOZD04MfMy3YQkINVsO0F0CaTpwZt9ZgG1a9WQPF3pxdZ/FjVI3T3EysN3RsJLr nirbDim1nVnhb5gpt5BhPX8fx6z6/frWygjLAKokCto9nvS3etMvRdd0SF/slHx+4Idk jHcA== X-Gm-Message-State: AGRZ1gL8STQQPKIzv7zjI3QQqvrntsso9s2SmAzl1uyn+Uqej9/GKhe8 wMgHbPmb6C9a8OuRRDMGfvDgctjR X-Google-Smtp-Source: AJdET5d7YTJpwHSYcYNgrWPK87wXNiL6Mb4XyeMIDEhEN7cHnhVao3sGmsc5NOYvxmFuomB0so94BQ== X-Received: by 2002:a67:784c:: with SMTP id t73mr1331530vsc.32.1540994257021; Wed, 31 Oct 2018 06:57:37 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id s85-v6sm2275624vse.29.2018.10.31.06.57.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 06:57:36 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.9 16/24] ARM: spectre-v1: add speculation barrier (csdb) macros Date: Wed, 31 Oct 2018 09:57:05 -0400 Message-Id: <20181031135713.2873-17-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031135713.2873-1-dave.long@linaro.org> References: <20181031135713.2873-1-dave.long@linaro.org> From: Russell King Commit a78d156587931a2c3b354534aa772febf6c9e855 upstream. Add assembly and C macros for the new CSDB instruction. Signed-off-by: Russell King Acked-by: Mark Rutland Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/assembler.h | 8 ++++++++ arch/arm/include/asm/barrier.h | 13 +++++++++++++ 2 files changed, 21 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 3aed4492c9a7..189f3b42baea 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -445,6 +445,14 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .size \name , . - \name .endm + .macro csdb +#ifdef CONFIG_THUMB2_KERNEL + .inst.w 0xf3af8014 +#else + .inst 0xe320f014 +#endif + .endm + .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req #ifndef CONFIG_CPU_USE_DOMAINS adds \tmp, \addr, #\size - 1 diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index f5d698182d50..6f00dac6ad8e 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -16,6 +16,12 @@ #define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory") #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") +#ifdef CONFIG_THUMB2_KERNEL +#define CSDB ".inst.w 0xf3af8014" +#else +#define CSDB ".inst 0xe320f014" +#endif +#define csdb() __asm__ __volatile__(CSDB : : : "memory") #elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ : : "r" (0) : "memory") @@ -36,6 +42,13 @@ #define dmb(x) __asm__ __volatile__ ("" : : : "memory") #endif +#ifndef CSDB +#define CSDB +#endif +#ifndef csdb +#define csdb() +#endif + #ifdef CONFIG_ARM_HEAVY_MB extern void (*soc_mb)(void); extern void arm_heavy_mb(void);