From patchwork Wed Oct 31 13:57:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Long X-Patchwork-Id: 149806 Delivered-To: patches@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp6826572ljp; Wed, 31 Oct 2018 06:57:32 -0700 (PDT) X-Received: by 2002:a9f:3743:: with SMTP id a3mr1446634uae.86.1540994252680; Wed, 31 Oct 2018 06:57:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1540994252; cv=none; d=google.com; s=arc-20160816; b=CUmRiCADH5ud+VpbNSVsTMjWGTAWiUjlJDNirV4O+cnb6ddfOkdDVEyvGuZV4OIxgZ GhVZR7CwUrksXWOI+bH4TVn8fHa3kxpKQiKmxX9qsSoTw5pffUR61gI7n6zbPjMW8Lk0 hlw8FBFnNqBSC5nOMJFxyQWMBOKLTVke1CURXC1uIuXaDDlKZrUCHSlyquM8QoXSly4o 8n+IZBDMPMANiX1c8rIKG3I2uTMbGAGJ1clJvQpdz7lWZdguM/YgZThFuTmzeuwUwRGh GhuvYpLDLYCOWYLjwvQs5z/0k0PAzqlQeNzaFRFfuk1LT86yztNxPevaYIWy/dDvyt71 gKVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1rW92+zw7W9hlx7da3odhtJaHCp6Wk4O4o7GmGLFBJU=; b=K6DojFMDUWhU9vJx20KYzZ+hyX31NQSgcIW0gMbb+0nkpFH9zZZzpOKNwiqFLcY4JB qU2jKy5qHxCxeiMrmoFcKRhiI8hQMG+TJziYtVoT0RDe9wzS4MptUdBbPG80mhlva7DF H0GyPSd2gcmiFA5oZDjPdx7Q8Y8w67C3ZXo/b8VwJvbxo+p6rWSUYOVOugTxyfMTAHQ0 fUGONpaqiolP5AwdO9T2OxPiQoi4550cPqtYuDntDBsta6PCaVHUnAjQedDDpr5UOM5j wwScsFKkVB9ER3T8T+Ti+UEAclvB4d4ciibsMeert6wSVy/CX0F9PfSaTE/21OM+QWpv lESw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JWU69/0i"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id i69sor13465393vkd.34.2018.10.31.06.57.32 for (Google Transport Security); Wed, 31 Oct 2018 06:57:32 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JWU69/0i"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1rW92+zw7W9hlx7da3odhtJaHCp6Wk4O4o7GmGLFBJU=; b=JWU69/0is00OSXiN611dVAWBfW7mGkm19QQHFSRTILPp/mFhJbXzwPfPgXrIWFkWIx IeaytD/BrfXjC7AqnXaoSs+CPrh9RGWTYpQHRHQxqY0EDjxRTN6YVDFe2+oJmnnZnFdT 8k2oWraT9y/dMNuiN3/TLx8xPaplLmLTWD93E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1rW92+zw7W9hlx7da3odhtJaHCp6Wk4O4o7GmGLFBJU=; b=NXMsB1iT4wHfjWNtsrnDfXApVASnDzTaQBbu4mk+LwIumzqWZhMXGFXQKg8U65SZ4L L9VWZrW5ccY1CK5cr1UYsuS/2MwHKCYZRKuEroLfrR+taCokheVdOaWYG0LG9iN3W/zc Hi0jNzb3rcV7CiguX8CIOkEtO9b0OeUhSjoQxyepdegrpRKvM5YcrtvFyqvZ/D0iRtYp LIf4ol0F4nKFoUQbIsuBrlnF3QuuAahlg4FiA36aiswvLcZ91d25iPUdjDtiS7wMIWiX XovYDYZ3OfqTrYlYVWqkMLORCXPJIXcrTlIJFJ2VSikcwncJg6S56agULqNLXLqPro6j G8JA== X-Gm-Message-State: AGRZ1gJmKJSfFxp0KNZM9FcoS2+DYfthWYqJTpfCow/Y0RGh2Ludbwqx mgjItBIfkcfxVhHhwaTZoi3fWzGv X-Google-Smtp-Source: AJdET5eNZELwOzPVC3U5uVWIRsgk+EbZDNXJUy1YVxcRbqXDo6uVtKIQH37WJ9x1gq4UfARdm3ZgIg== X-Received: by 2002:a1f:8892:: with SMTP id k140mr1307219vkd.50.1540994252051; Wed, 31 Oct 2018 06:57:32 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id s85-v6sm2275624vse.29.2018.10.31.06.57.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 06:57:31 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.9 12/24] ARM: KVM: invalidate icache on guest exit for Cortex-A15 Date: Wed, 31 Oct 2018 09:57:01 -0400 Message-Id: <20181031135713.2873-13-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031135713.2873-1-dave.long@linaro.org> References: <20181031135713.2873-1-dave.long@linaro.org> From: Marc Zyngier Commit 0c47ac8cd157727e7a532d665d6fb1b5fd333977 upstream. In order to avoid aliasing attacks against the branch predictor on Cortex-A15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. Signed-off-by: Marc Zyngier Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: David A. Long --- arch/arm/include/asm/kvm_mmu.h | 5 +++++ arch/arm/kvm/hyp/hyp-entry.S | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) -- 2.17.1 diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 625edef2a54f..3ad2c44f4137 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -257,6 +257,11 @@ static inline void *kvm_get_hyp_vector(void) return kvm_ksym_ref(__kvm_hyp_vector_bp_inv); } + case ARM_CPU_PART_CORTEX_A15: + { + extern char __kvm_hyp_vector_ic_inv[]; + return kvm_ksym_ref(__kvm_hyp_vector_ic_inv); + } #endif default: { diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S index de242d9598c6..582f50759d80 100644 --- a/arch/arm/kvm/hyp/hyp-entry.S +++ b/arch/arm/kvm/hyp/hyp-entry.S @@ -72,6 +72,28 @@ __kvm_hyp_vector: W(b) hyp_fiq #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + .align 5 +__kvm_hyp_vector_ic_inv: + .global __kvm_hyp_vector_ic_inv + + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + W(add) sp, sp, #1 /* Reset 7 */ + W(add) sp, sp, #1 /* Undef 6 */ + W(add) sp, sp, #1 /* Syscall 5 */ + W(add) sp, sp, #1 /* Prefetch abort 4 */ + W(add) sp, sp, #1 /* Data abort 3 */ + W(add) sp, sp, #1 /* HVC 2 */ + W(add) sp, sp, #1 /* IRQ 1 */ + W(nop) /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + .align 5 __kvm_hyp_vector_bp_inv: .global __kvm_hyp_vector_bp_inv @@ -92,6 +114,8 @@ __kvm_hyp_vector_bp_inv: mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: + #ifdef CONFIG_THUMB2_KERNEL /* * Yet another silly hack: Use VPIDR as a temp register.