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[209.85.220.65]) by mx.google.com with SMTPS id x85-v6sor13408542vke.58.2018.10.31.06.57.30 for (Google Transport Security); Wed, 31 Oct 2018 06:57:30 -0700 (PDT) Received-SPF: pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gDg4/PMO"; spf=pass (google.com: domain of dave.long@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=dave.long@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PtvOdRYgxdWqiincDIf4CTD/BFKZK9uYA9vLMv5udX0=; b=gDg4/PMOe+W1iZ7HwdeEr5jxB4BcSeBPUG3Idx0DWP4zHiDpe1CzJtbuJRj35GTNQX L6R4ojbBr91WyezGNIk/BujUU/c+QsbWa4LnkLvLYP6v0eOwoLhdehdWlxZ0I4eGPkoV QxITeyMBL/35MuRJsoTosObzUvAH6zppd87Ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PtvOdRYgxdWqiincDIf4CTD/BFKZK9uYA9vLMv5udX0=; b=Sz39PnmGiRD+gc5npdQbGBqDdrRWSGn5kZUGRg1oPaW55hJHByzVHh/M1eT/YRsIKp jEHu/Xx5jr+1AJwJY807Pnpx/upY+UEZyvQF+s2k+Aw6spj527ek+WrnFHFqe68ei+1z 6Ydw/Mw8nGp7UHNE4JY/k53e8HTSwSaC+SwGSuwgPtFcMjIcsBoiqAopx37gz1HRZLOy 5D2ZAxsnB7TrJRTH+HAlJJaCcjGy9bWk/ch8N68v2hTDHZ1Q40un7t9xXpjTIUtDP+iA tn1V5SRJGrGPBwPQ+Z8bo0Zl36M6tmUqSTki68WST303J4HErhMt5UKlXJhMV1nfbcjc /NkQ== X-Gm-Message-State: AGRZ1gI2FN4GaLEq2ePx/3mM+0opjPGFO1/Vk8GjtOyGJsZGLbIqq6nr 8FMddiooB6HnStK3/7ezeJTVFf5P X-Google-Smtp-Source: AJdET5fJmhi1SKGq4jch9eonuXq4p9If+CatOLnYZe8ANRlFBKlu9qKRVbEHXosV7K6YyBeV6qZu9w== X-Received: by 2002:a1f:8b48:: with SMTP id n69-v6mr1305237vkd.78.1540994249532; Wed, 31 Oct 2018 06:57:29 -0700 (PDT) Return-Path: Received: from dave-Dell-System-XPS-L502X.hsd1.nh.comcast.net ([2603:3005:3403:7100:2c71:8680:34e1:a6aa]) by smtp.googlemail.com with ESMTPSA id s85-v6sm2275624vse.29.2018.10.31.06.57.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Oct 2018 06:57:29 -0700 (PDT) From: David Long To: stable@vger.kernel.org, Russell King - ARM Linux , Florian Fainelli , Tony Lindgren , Marc Zyngier , Mark Rutland Cc: Greg KH , Mark Brown Subject: [PATCH 4.9 10/24] ARM: spectre-v2: warn about incorrect context switching functions Date: Wed, 31 Oct 2018 09:56:59 -0400 Message-Id: <20181031135713.2873-11-dave.long@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181031135713.2873-1-dave.long@linaro.org> References: <20181031135713.2873-1-dave.long@linaro.org> From: Russell King Commit c44f366ea7c85e1be27d08f2f0880f4120698125 upstream. Warn at error level if the context switching function is not what we are expecting. This can happen with big.Little systems, which we currently do not support. Signed-off-by: Russell King Boot-tested-by: Tony Lindgren Reviewed-by: Tony Lindgren Acked-by: Marc Zyngier Signed-off-by: David A. Long --- arch/arm/mm/proc-v7-bugs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.17.1 diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c index da25a38e1897..5544b82a2e7a 100644 --- a/arch/arm/mm/proc-v7-bugs.c +++ b/arch/arm/mm/proc-v7-bugs.c @@ -12,6 +12,8 @@ #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); +extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); +extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); @@ -50,6 +52,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A17: case ARM_CPU_PART_CORTEX_A73: case ARM_CPU_PART_CORTEX_A75: + if (processor.switch_mm != cpu_v7_bpiall_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_bpiall; spectre_v2_method = "BPIALL"; @@ -57,6 +61,8 @@ static void cpu_v7_spectre_init(void) case ARM_CPU_PART_CORTEX_A15: case ARM_CPU_PART_BRAHMA_B15: + if (processor.switch_mm != cpu_v7_iciallu_switch_mm) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = harden_branch_predictor_iciallu; spectre_v2_method = "ICIALLU"; @@ -82,6 +88,8 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; + if (processor.switch_mm != cpu_v7_hvc_switch_mm && cpu) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_hvc_arch_workaround_1; processor.switch_mm = cpu_v7_hvc_switch_mm; @@ -93,6 +101,8 @@ static void cpu_v7_spectre_init(void) ARM_SMCCC_ARCH_WORKAROUND_1, &res); if ((int)res.a0 != 0) break; + if (processor.switch_mm != cpu_v7_smc_switch_mm && cpu) + goto bl_error; per_cpu(harden_branch_predictor_fn, cpu) = call_smc_arch_workaround_1; processor.switch_mm = cpu_v7_smc_switch_mm; @@ -109,6 +119,11 @@ static void cpu_v7_spectre_init(void) if (spectre_v2_method) pr_info("CPU%u: Spectre v2: using %s workaround\n", smp_processor_id(), spectre_v2_method); + return; + +bl_error: + pr_err("CPU%u: Spectre v2: incorrect context switching function, system vulnerable\n", + cpu); } #else static void cpu_v7_spectre_init(void)