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[209.132.180.67]) by mx.google.com with ESMTP id h132si12820449pfe.52.2018.04.17.01.53.22; Tue, 17 Apr 2018 01:53:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VxIo7m/7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752557AbeDQIxU (ORCPT + 11 others); Tue, 17 Apr 2018 04:53:20 -0400 Received: from mail-lf0-f68.google.com ([209.85.215.68]:38933 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752320AbeDQIxR (ORCPT ); Tue, 17 Apr 2018 04:53:17 -0400 Received: by mail-lf0-f68.google.com with SMTP id p142-v6so26134775lfd.6 for ; Tue, 17 Apr 2018 01:53:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=v0XA68wAX8uR4hsDI32l8U6R9/ljzh9/XLywRtLAwCA=; b=VxIo7m/7rYBjok6rhnTvx/BrI6zfLsna6MBchYf6WIv8+DgkjJpJ9Sgvp3AhOywAx5 p0FFWoI/M66yILBV8WiCA+W6wSzge6aKXKZjejuyQdGrrIEYMf03Jj+CVEK81E4K1xXv ZLQ9ztOeFA56pU5vm0/B/Yn6TfSNgEyuvyiEE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=v0XA68wAX8uR4hsDI32l8U6R9/ljzh9/XLywRtLAwCA=; b=KQ3vQthZkARjIWQuO3mktKiUUc1phXR9UD/DFbruTX2nW4EihrRbd045+HEPIQbS4M D5L/9RAhiZQQy8aE5JZeQaBq1ANQAJd/MMABwKy3UA7BBImclCyZNaC0BWSULS3PKszW Kd/Xi8n2t2NS/kEBx1M+lF9KtzH2kYBsjmwlpMa5fAT1snULrWQ9RsDtHa7dkG9Z9P84 8D9/gOqvgmEgeLdlCxVDvLOkLMvSKaaeUacdnVOp494kgPxHV+dP6gTyKEQd2nncHUwO 2eKRECyVK28oHaD6Q7laoObuoCpKiuyzv5yphnl4wXwDdoyFGCjivMDRwQE+K7GFxIbk qI0Q== X-Gm-Message-State: ALQs6tBZ2B8wDnMvNf6g12o/9J1202vASfdNXYXlcyF2A7qLwF8JgHMm GMq7PXYKauHwpL7zCRbcwmG8cQbsPu8= X-Received: by 10.46.91.21 with SMTP id p21mr926794ljb.38.1523955196140; Tue, 17 Apr 2018 01:53:16 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id k185-v6sm3264510lfe.96.2018.04.17.01.53.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 17 Apr 2018 01:53:15 -0700 (PDT) From: Linus Walleij To: arm@kernel.org, Andreas Fiedler , Roman Yeryomin Cc: linux-arm-kernel@lists.infradead.org, Linus Walleij , stable@vger.kernel.org, Hans Ulli Kroll Subject: [PATCH] ARM: dts: Fix NAS4220B pin config Date: Tue, 17 Apr 2018 10:53:11 +0200 Message-Id: <20180417085311.13829-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The DTS file for the NAS4220B had the pin config for the ethernet interface set to the pins in the SL3512 SoC while this system is using SL3516. Fix it by referencing the right SL3516 pins instead of the SL3512 pins. Cc: stable@vger.kernel.org Cc: Hans Ulli Kroll Reported-by: Andreas Fiedler Reported-by: Roman Yeryomin Signed-off-by: Linus Walleij --- Hi ARM SoC folks: if this gets a Tested-by or similar from someone with the NAS4220B please apply it directly to the ARM SoC tree for fixes. --- arch/arm/boot/dts/gemini-nas4220b.dts | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.14.3 Tested-by: Roman Yeryomin diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts index 8bbb6f85d161..4785fbcc41ed 100644 --- a/arch/arm/boot/dts/gemini-nas4220b.dts +++ b/arch/arm/boot/dts/gemini-nas4220b.dts @@ -134,37 +134,37 @@ function = "gmii"; groups = "gmii_gmac0_grp"; }; - /* Settings come from OpenWRT */ + /* Settings come from OpenWRT, pins on SL3516 */ conf0 { - pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; + pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV"; skew-delay = <0>; }; conf1 { - pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC"; + pins = "Y7 GMAC0 RXC", "Y11 GMAC1 RXC"; skew-delay = <15>; }; conf2 { - pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; + pins = "T8 GMAC0 TXEN", "W11 GMAC1 TXEN"; skew-delay = <7>; }; conf3 { - pins = "V7 GMAC0 TXC"; + pins = "U8 GMAC0 TXC"; skew-delay = <11>; }; conf4 { - pins = "P10 GMAC1 TXC"; + pins = "V11 GMAC1 TXC"; skew-delay = <10>; }; conf5 { /* The data lines all have default skew */ - pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", - "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", - "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", - "R7 GMAC0 TXD2", "P7 GMAC0 TXD3", - "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", - "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", - "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", - "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; + pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1", + "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3", + "T7 GMAC0 TXD0", "U6 GMAC0 TXD1", + "V7 GMAC0 TXD2", "U7 GMAC0 TXD3", + "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1", + "T11 GMAC1 RXD2", "W12 GMAC1 RXD3", + "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1", + "W10 GMAC1 TXD2", "T9 GMAC1 TXD3"; skew-delay = <7>; }; /* Set up drive strength on GMAC0 to 16 mA */