From patchwork Tue Apr 3 11:08:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 132713 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3665492ljb; Tue, 3 Apr 2018 04:09:47 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+iK006fakzKdF1dKbFpxpRw+mx0RTIHyTHY8zYSQymY2n34q6kcxjO5PV58+nTBRPl/WV6 X-Received: by 2002:a17:902:7084:: with SMTP id z4-v6mr14103250plk.395.1522753787297; Tue, 03 Apr 2018 04:09:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522753787; cv=none; d=google.com; s=arc-20160816; b=0V065MhbIes6CmBaHpz0MIGjeoSXOECFR7F8L8itNBA/fjU4Re90QEcDXYiiIRpkk4 9SsfYTvuh5p1vepNWJjTN9HOMcvE9sl96zZ0U12mnLl0KuOpthTjW73IModSqXS2n2K0 K1rnQDM/Y1j1jhla+VpFY3BG9GukiEftYUYg0oZKQfoybnXgnfnBZGH9VecuCecDUUhN dOIRLwQw90aixFJ9JBgg57r5NdGHmV73uDxcA5HOWxNFhVYiZczyBV/VuRtvKJBM0VdN Tv3JCpI34ZDR7f6IgQJwqeW+k6+qdEvPjDhJggBKoUID+45IxGiZCzim4xcZ0Y7xA6ov Bs8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=4Ve8vJXvE4K0iWNHu/gh8BISMn0rrIS+L+xpS3MqlgU=; b=zAuwjCGLWiUepXhAPzhrnXVDVRjbSN+42lBWbo+dEH/NBReYOMrrHHRMLe4RxVNxbi 0AxuaJ81iQuI2OzumsmWawJ25iOqHIcbjq+Y3Y0jkTJi7qaPyXBG0GOhUEDZsL3zCaR8 FaQ3c3FLPEHlNaziUdY0NJdFyF4tYxmiMZbSf+1/Sl1P20SbIgp8GUK9f2WMQTsAj3ft giLSL/3LNQhqHLtxY0fLYu58Hy7Qu5C/prczG+E74ii7jjKzogrof8OcgHxIuW006jMn hE+/KlOs1YjM90QqbnzEEygBz6p64IbZRs5JyiPh3tb504l1HRbfZepxS5oOwTbKAYx9 FSHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d14-v6si302866plj.191.2018.04.03.04.09.47; Tue, 03 Apr 2018 04:09:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754994AbeDCLJq (ORCPT + 11 others); Tue, 3 Apr 2018 07:09:46 -0400 Received: from foss.arm.com ([217.140.101.70]:59284 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754869AbeDCLJq (ORCPT ); Tue, 3 Apr 2018 07:09:46 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EEB8E1435; Tue, 3 Apr 2018 04:09:45 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BE0D13F587; Tue, 3 Apr 2018 04:09:44 -0700 (PDT) From: Mark Rutland To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com Subject: [PATCH v4.9.y 02/27] arm64: mm: Move ASID from TTBR0 to TTBR1 Date: Tue, 3 Apr 2018 12:08:58 +0100 Message-Id: <20180403110923.43575-3-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180403110923.43575-1-mark.rutland@arm.com> References: <20180403110923.43575-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 7655abb95386 upstream. In preparation for mapping kernelspace and userspace with different ASIDs, move the ASID to TTBR1 and update switch_mm to context-switch TTBR0 via an invalid mapping (the zero page). Reviewed-by: Mark Rutland Tested-by: Laura Abbott Tested-by: Shanker Donthineni Signed-off-by: Will Deacon Signed-off-by: Alex Shi [v4.9 backport] Signed-off-by: Mark Rutland [v4.9 backport] --- arch/arm64/include/asm/mmu_context.h | 7 +++++++ arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/include/asm/proc-fns.h | 6 ------ arch/arm64/mm/proc.S | 9 ++++++--- 4 files changed, 14 insertions(+), 9 deletions(-) -- 2.11.0 diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index a50185375f09..b96c4799f881 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -50,6 +50,13 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } +static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) +{ + BUG_ON(pgd == swapper_pg_dir); + cpu_set_reserved_ttbr0(); + cpu_do_switch_mm(virt_to_phys(pgd),mm); +} + /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index eb0c2bd90de9..8df4cb6ac6f7 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,6 +272,7 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) +#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h index 14ad6e4e87d1..16cef2e8449e 100644 --- a/arch/arm64/include/asm/proc-fns.h +++ b/arch/arm64/include/asm/proc-fns.h @@ -35,12 +35,6 @@ extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include -#define cpu_switch_mm(pgd,mm) \ -do { \ - BUG_ON(pgd == swapper_pg_dir); \ - cpu_do_switch_mm(virt_to_phys(pgd),mm); \ -} while (0) - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 352c73b6a59e..3378f3e21224 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -132,9 +132,12 @@ ENDPROC(cpu_do_resume) * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) + mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 + bfi x2, x1, #48, #16 // set the ASID + msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + isb + msr ttbr0_el1, x0 // now update TTBR0 isb alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu @@ -222,7 +225,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 tcr_set_idmap_t0sz x10, x9 /*