From patchwork Tue Apr 3 11:09:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 132734 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp3666680ljb; Tue, 3 Apr 2018 04:10:49 -0700 (PDT) X-Google-Smtp-Source: AIpwx48E/EfNzzZNLDxgUNnkKsKdnIyYaO5G+nCzJhP4Wk3TCADRoyEYdRCiFlQ1jkDlvuMbUEIr X-Received: by 2002:a17:902:228:: with SMTP id 37-v6mr13732543plc.141.1522753849005; Tue, 03 Apr 2018 04:10:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522753849; cv=none; d=google.com; s=arc-20160816; b=Y5NeK0aUTs4v2stXkvKwUBzF1WCx+askzbMuVxyW05l6Zydo22Wg80Ebpi1jneH4Cn Oljzbi0uQfJnRSFZb23tJZy2SCYF/OHUePWAEi2bs7VNfcuEBdunzWdg/vGNqDQ93FNO 5nehHw5+ALUXF8aYeEs1vnLOXmcDxbvt/zowSm5ErnRC7ypcN8pR09vBKbtkE0QmN4oU PCXdiYWVgj6/e3UhkgI1Ts1+7Vge2tEOmItx1F8XAF0/UUxuS4zdokpvfXdmGwQdJnYk JJtgDwlyEbHbDUgZf41HJsLdS32GiqjQib96wb1Bh9VD/ivzgfE9NoZ1eFJg03IxNGKq NRGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VlZJmP5LbalzgNv22QGek8nUbG/L58GGQ8kJyIqh1Yw=; b=jwwW/VkxmgcfKAqEbS/Fs7dDjq1j/F0bIDCFgRPqWKn+YQxmOXTJDcuMowUxA38T61 7vmj9qRBVvL5fZN8o6xLmALc0b243tcFNyXBk9XAn7Ze1gJ3m7mpF9FQrKoB0lAK77v9 sBjBJ+GPRXkSV/PtmL9POPLhasx1EZO1wTUXgdV2lcOsRM/+G8LP/LAakg6zSEfIObgi 78UKgi+5O+Mza5flPUo7mgWJbsa49CudHoMGbLm3m4H0DB9M8S9oFy6qeXurot8fBEQ9 pNFLw3sRKgwn0uzPJK5VAufL+JtlA2c+rv9Cz0kX9hM42P8cTb451TPbcyOgcamdq1LV qQEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q9-v6si295691plr.273.2018.04.03.04.10.48; Tue, 03 Apr 2018 04:10:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755427AbeDCLK3 (ORCPT + 11 others); Tue, 3 Apr 2018 07:10:29 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59400 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755252AbeDCLK2 (ORCPT ); Tue, 3 Apr 2018 07:10:28 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90C4E1435; Tue, 3 Apr 2018 04:10:27 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 602B43F587; Tue, 3 Apr 2018 04:10:26 -0700 (PDT) From: Mark Rutland To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com Subject: [PATCH v4.9.y 21/27] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Tue, 3 Apr 2018 12:09:17 +0100 Message-Id: <20180403110923.43575-22-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180403110923.43575-1-mark.rutland@arm.com> References: <20180403110923.43575-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit 0d90718871fe upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Alex Shi [v4.9 backport] Signed-off-by: Mark Rutland [v4.9 backport] --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 26a68ddb11c1..1d47930c30dc 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -81,6 +81,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -88,6 +89,8 @@ #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #ifndef __ASSEMBLY__